/* Added by Zephyr: recent Cadence headers want UINT32_C, but don't
 * include stdint.h (and the toolchain stdint.h isn't asm-compatible
 * anyway
 */
#ifndef UINT32_C
#ifdef _ASMLANGUAGE
#define UINT32_C(x) x
#else
#define UINT32_C(x) x##UL
#endif
#endif
/* 
 * xtensa/config/core.h -- HAL definitions dependent on CORE configuration
 *
 *  This header file is sometimes referred to as the "compile-time HAL" or CHAL.
 *  It pulls definitions tailored for a specific Xtensa processor configuration.
 *
 *  Sources for binaries meant to be configuration-independent generally avoid
 *  including this file (they may use the configuration-specific HAL library).
 *  It is normal for the HAL library source itself to include this file.
 */

/*
 * Copyright (c) 2005-2016 Cadence Design Systems, Inc.
 *
 * Permission is hereby granted, free of charge, to any person obtaining
 * a copy of this software and associated documentation files (the
 * "Software"), to deal in the Software without restriction, including
 * without limitation the rights to use, copy, modify, merge, publish,
 * distribute, sublicense, and/or sell copies of the Software, and to
 * permit persons to whom the Software is furnished to do so, subject to
 * the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
 * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 */


#ifndef XTENSA_CONFIG_CORE_H
#define XTENSA_CONFIG_CORE_H

/*  CONFIGURATION INDEPENDENT DEFINITIONS:  */
#ifdef __XTENSA__
#include <xtensa/hal.h>
#include <xtensa/xtensa-versions.h>
#include <xtensa/xtensa-types.h>
#else
#include "../hal.h"
#include "../xtensa-versions.h"
#include "../xtensa-types.h"
#endif

/*  CONFIGURATION SPECIFIC DEFINITIONS:  */
#ifdef __XTENSA__
#include <xtensa/config/core-isa.h>
#include <xtensa/config/core-matmap.h>
#include <xtensa/config/tie.h>
#else
#include "core-isa.h"
#include "core-matmap.h"
#include "tie.h"
#endif

#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)
#ifdef __XTENSA__
#include <xtensa/coreasm.h>
#include <xtensa/config/tie-asm.h>
#else
#include "coreasm.h"
#include "tie-asm.h"
#endif
#endif /*_ASMLANGUAGE or __ASSEMBLER__*/


/*----------------------------------------------------------------------
				GENERAL
  ----------------------------------------------------------------------*/

/*
 *  Separators for macros that expand into arrays.
 *  These can be predefined by files that #include this one,
 *  when different separators are required.
 */
/*  Element separator for macros that expand into 1-dimensional arrays:  */
#ifndef XCHAL_SEP
#define XCHAL_SEP			,
#endif
/*  Array separator for macros that expand into 2-dimensional arrays:  */
#ifndef XCHAL_SEP2
#define XCHAL_SEP2			},{
#endif

/*  Variadic macros for indexing and selecting.  */

/*  For MSVC:  */
#define XCHAL_EXPAND(x)       x

/*  XCHAL_SELECT(n, ...) expands argument 'n' (0..19) of '...'.  */
#define XCHAL__0(x, ...) x
#define XCHAL__1(a, x, ...) x
#define XCHAL__2(a,b, x, ...) x
#define XCHAL__3(a,b,c, x, ...) x
#define XCHAL__4(a,b,c,d, x, ...) x
#define XCHAL__5(a,b,c,d,e, x, ...) x
#define XCHAL__6(a,b,c,d,e,f, x, ...) x
#define XCHAL__7(a,b,c,d,e,f,g, x, ...) x
#define XCHAL__8(a,b,c,d,e,f,g,h, x, ...) x
#define XCHAL__9(a,b,c,d,e,f,g,h,i, x, ...) x
#define XCHAL__10(a,b,c,d,e,f,g,h,i,j, x, ...) x
#define XCHAL__11(a,b,c,d,e,f,g,h,i,j,k, x, ...) x
#define XCHAL__12(a,b,c,d,e,f,g,h,i,j,k,l, x, ...) x
#define XCHAL__13(a,b,c,d,e,f,g,h,i,j,k,l,m, x, ...) x
#define XCHAL__14(a,b,c,d,e,f,g,h,i,j,k,l,m,n, x, ...) x
#define XCHAL__15(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o, x, ...) x
#define XCHAL__16(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p, x, ...) x
#define XCHAL__17(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q, x, ...) x
#define XCHAL__18(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r, x, ...) x
#define XCHAL__19(a,b,c,d,e,f,g,h,i,j,k,l,m,n,o,p,q,r,s, x, ...) x
#define XCHAL__SELECT(n, ...) XCHAL__ ## n(__VA_ARGS__, dummy) 	// PRQA S 0342 # suppress MISRA RULE-20.10 "Using the glue operator ##"
#define XCHAL_SELECT(n, ...)  XCHAL_EXPAND(XCHAL__SELECT(n, __VA_ARGS__))


/*----------------------------------------------------------------------
                                ERRATA
  ----------------------------------------------------------------------*/

/*
 *  Erratum 453 present in RE-2013.2 up to RF-2014.0, fixed in RF-2014.1.
 *  Applies to specific set of configuration options.
 *  Part of the workaround is to add ISYNC at certain points in the code.
 *  The workaround gated by this macro can be disabled if not needed, e.g. if
 *  zero-overhead loop buffer will be disabled, by defining _NO_ERRATUM_453.
 */
#if (   XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2013_2 && \
        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2014_0 && \
        XCHAL_ICACHE_SIZE != 0    && XCHAL_HAVE_PIF /*covers also AXI/AHB*/ && \
        XCHAL_HAVE_LOOPS          && XCHAL_LOOP_BUFFER_SIZE != 0 && \
        XCHAL_CLOCK_GATING_GLOBAL && !defined(_NO_ERRATUM_453) )
#define XCHAL_ERRATUM_453       1
#else
#define XCHAL_ERRATUM_453       0
#endif

/*
 *  Erratum 497 present in RE-2012.2 up to RG/RF-2015.2
 *  Applies to specific set of configuration options.
 *  Workaround is to add MEMWs after at most 8 cache WB instructions
 */
#if ( ((XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RE_2012_0 &&    \
        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RF_2015_2) ||   \
       (XCHAL_HW_MAX_VERSION >= XTENSA_HWVERSION_RG_2015_0 &&    \
        XCHAL_HW_MIN_VERSION <= XTENSA_HWVERSION_RG_2015_2)     \
      ) && \
      XCHAL_DCACHE_IS_WRITEBACK && \
      XCHAL_HAVE_AXI && \
      XCHAL_HAVE_PIF_WR_RESP && \
      XCHAL_HAVE_PIF_REQ_ATTR &&  !defined(_NO_ERRATUM_497) \
    )
#define XCHAL_ERRATUM_497       1
#else
#define XCHAL_ERRATUM_497       0
#endif


/*----------------------------------------------------------------------
				ISA
  ----------------------------------------------------------------------*/

#if XCHAL_HAVE_BE
# define XCHAL_HAVE_LE			0
# define XCHAL_MEMORY_ORDER		XTHAL_BIGENDIAN
#else
# define XCHAL_HAVE_LE			1
# define XCHAL_MEMORY_ORDER		XTHAL_LITTLEENDIAN
#endif



/*----------------------------------------------------------------------
                         HARDWARE FLOATING POINT
  ----------------------------------------------------------------------*/

#if (XCHAL_HAVE_FP)                   || \
    (XCHAL_HAVE_HIFI3_VFPU == 1)      || \
    (XCHAL_HAVE_HIFI4_VFPU == 1)      || \
    (XCHAL_HAVE_FUSION_FP == 1)       || \
    (XCHAL_HAVE_CONNX_B_SP_VFPU == 1) || \
    ((XCHAL_HAVE_FUSIONG3 == 1) && (XCHAL_HAVE_USER_SPFPU == 1)) || \
    ((XCHAL_HAVE_FUSIONG6 == 1) && (XCHAL_HAVE_USER_SPFPU == 1)) || \
    ((XCHAL_HAVE_FUSIONJ6 == 1) && (XCHAL_HAVE_USER_SPFPU == 1)) || \
    ((XCHAL_HAVE_PDX4 == 1)     && (XCHAL_HAVE_FUSIONG3 == 0))   || \
    ((XCHAL_HAVE_PDXNX == 1)    && (XCHAL_HAVE_FUSIONJ6 == 0) && (XCHAL_PDX_SIMD32 == 8)) || \
    ((XCHAL_VISION_TYPE >= 6)   && (XCHAL_HAVE_VISION_SP_VFPU == 1)) || \
    ((XCHAL_HAVE_BBENEP == 1)   && (XCHAL_HAVE_BBENEP_SP_VFPU == 1))
# define XCHAL_HAVE_HWFP		1
#else
# define XCHAL_HAVE_HWFP		0
#endif


/*----------------------------------------------------------------------
				INTERRUPTS
  ----------------------------------------------------------------------*/

/*  Indexing macros:  */
// PRQA S 0342 ++ # begin-suppress MISRA RULE-20.10 "Using the glue operator ##"
#define I_XCHAL_INTLEVEL_MASK(n)		XCHAL_INTLEVEL ## n ## _MASK
#define XCHAL_INTLEVEL_MASK(n)			I_XCHAL_INTLEVEL_MASK(n)		/* n = 0 .. 15 */
#if XCHAL_NUM_INTERRUPTS > 32
#define I_XCHAL_INTLEVEL_MASK1(n)		XCHAL_INTLEVEL ## n ## _MASK1
#define XCHAL_INTLEVEL_MASK1(n)			I_XCHAL_INTLEVEL_MASK1(n)		/* n = 0 .. 15 */
#define I_XCHAL_INTLEVEL_MASK2(n)		XCHAL_INTLEVEL ## n ## _MASK2
#define XCHAL_INTLEVEL_MASK2(n)			I_XCHAL_INTLEVEL_MASK2(n)		/* n = 0 .. 15 */
#define I_XCHAL_INTLEVEL_MASK3(n)		XCHAL_INTLEVEL ## n ## _MASK3
#define XCHAL_INTLEVEL_MASK3(n)			I_XCHAL_INTLEVEL_MASK3(n)		/* n = 0 .. 15 */
#endif
#define I_XCHAL_INTLEVEL_ANDBELOWMASK(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK
#define XCHAL_INTLEVEL_ANDBELOW_MASK(n)		I_XCHAL_INTLEVEL_ANDBELOWMASK(n)	/* n = 0 .. 15 */
#if XCHAL_NUM_INTERRUPTS > 32
#define I_XCHAL_INTLEVEL_ANDBELOWMASK1(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK1
#define XCHAL_INTLEVEL_ANDBELOW_MASK1(n)	I_XCHAL_INTLEVEL_ANDBELOWMASK1(n)	/* n = 0 .. 15 */
#define I_XCHAL_INTLEVEL_ANDBELOWMASK2(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK2
#define XCHAL_INTLEVEL_ANDBELOW_MASK2(n)	I_XCHAL_INTLEVEL_ANDBELOWMASK2(n)	/* n = 0 .. 15 */
#define I_XCHAL_INTLEVEL_ANDBELOWMASK3(n)	XCHAL_INTLEVEL ## n ## _ANDBELOW_MASK3
#define XCHAL_INTLEVEL_ANDBELOW_MASK3(n)	I_XCHAL_INTLEVEL_ANDBELOWMASK3(n)	/* n = 0 .. 15 */
#endif
#define I_XCHAL_INTLEVEL_NUM(n)			XCHAL_INTLEVEL ## n ## _NUM
#define XCHAL_INTLEVEL_NUM(n)			I_XCHAL_INTLEVEL_NUM(n)			/* n = 0 .. 15 */
#define I_XCHAL_INT_LEVEL(n)			XCHAL_INT ## n ## _LEVEL
#define XCHAL_INT_LEVEL(n)			I_XCHAL_INT_LEVEL(n)			/* n = 0 .. 127 */
#define I_XCHAL_INT_TYPE(n)			XCHAL_INT ## n ## _TYPE
#define XCHAL_INT_TYPE(n)			I_XCHAL_INT_TYPE(n)			/* n = 0 .. 127 */
#define I_XCHAL_TIMER_INTERRUPT(n)		XCHAL_TIMER ## n ## _INTERRUPT
#define XCHAL_TIMER_INTERRUPT(n)		I_XCHAL_TIMER_INTERRUPT(n)		/* n = 0 .. 3 */
// PRQA S 0342 -- # end-suppress MISRA RULE-20.10 "Using the glue operator ##"

#define XCHAL_HAVE_HIGHLEVEL_INTERRUPTS	XCHAL_HAVE_HIGHPRI_INTERRUPTS
#define XCHAL_NUM_LOWPRI_LEVELS		1			/* number of low-priority interrupt levels (always 1) */
#define XCHAL_FIRST_HIGHPRI_LEVEL	(XCHAL_NUM_LOWPRI_LEVELS+1)	/* level of first high-priority interrupt (always 2) */
/*  Note:  1 <= LOWPRI_LEVELS <= EXCM_LEVEL < DEBUGLEVEL <= NUM_INTLEVELS < NMILEVEL <= 15  */

/*  These values are constant for existing Xtensa processor implementations:  */
#if XCHAL_HAVE_XEA2

#define XCHAL_INTLEVEL0_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL8_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL9_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL10_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL11_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL12_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL13_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL14_MASK		UINT32_C(0x00000000)
#define XCHAL_INTLEVEL15_MASK		UINT32_C(0x00000000)

/*  Array of masks of interrupts at each interrupt level:  */
#define XCHAL_INTLEVEL_MASKS		XCHAL_INTLEVEL0_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL1_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL2_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL3_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL4_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL5_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL6_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL7_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL8_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL9_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL10_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL11_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL12_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL13_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL14_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL15_MASK

/*  These values are constant for existing Xtensa processor implementations:  */
#define XCHAL_INTLEVEL0_ANDBELOW_MASK	UINT32_C(0x00000000)
#define XCHAL_INTLEVEL8_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL9_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL10_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL11_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL12_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL13_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL14_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK
#define XCHAL_INTLEVEL15_ANDBELOW_MASK	XCHAL_INTLEVEL7_ANDBELOW_MASK

/*  Mask of all low-priority interrupts:  */
#define XCHAL_LOWPRI_MASK		XCHAL_INTLEVEL1_ANDBELOW_MASK

/*  Mask of all interrupts masked by PS.EXCM (or CEXCM):  */
#define XCHAL_EXCM_MASK			XCHAL_INTLEVEL_ANDBELOW_MASK(XCHAL_EXCM_LEVEL)

/*  Array of masks of interrupts at each range 1..n of interrupt levels:  */
#define XCHAL_INTLEVEL_ANDBELOW_MASKS	XCHAL_INTLEVEL0_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL1_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL2_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL3_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL4_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL5_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL6_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL7_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL8_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL9_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL10_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL11_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL12_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL13_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL14_ANDBELOW_MASK \
			XCHAL_SEP	XCHAL_INTLEVEL15_ANDBELOW_MASK

#if 0 /*XCHAL_HAVE_NMI*/
/*  NMI "interrupt level" (for use with EXCSAVE_n, EPS_n, EPC_n, RFI n):  */
# define XCHAL_NMILEVEL		(XCHAL_NUM_INTLEVELS+1)
#endif

/*  Array of levels of each possible interrupt:  */
#define XCHAL_INT_LEVELS		XCHAL_INT0_LEVEL \
			XCHAL_SEP	XCHAL_INT1_LEVEL \
			XCHAL_SEP	XCHAL_INT2_LEVEL \
			XCHAL_SEP	XCHAL_INT3_LEVEL \
			XCHAL_SEP	XCHAL_INT4_LEVEL \
			XCHAL_SEP	XCHAL_INT5_LEVEL \
			XCHAL_SEP	XCHAL_INT6_LEVEL \
			XCHAL_SEP	XCHAL_INT7_LEVEL \
			XCHAL_SEP	XCHAL_INT8_LEVEL \
			XCHAL_SEP	XCHAL_INT9_LEVEL \
			XCHAL_SEP	XCHAL_INT10_LEVEL \
			XCHAL_SEP	XCHAL_INT11_LEVEL \
			XCHAL_SEP	XCHAL_INT12_LEVEL \
			XCHAL_SEP	XCHAL_INT13_LEVEL \
			XCHAL_SEP	XCHAL_INT14_LEVEL \
			XCHAL_SEP	XCHAL_INT15_LEVEL \
			XCHAL_SEP	XCHAL_INT16_LEVEL \
			XCHAL_SEP	XCHAL_INT17_LEVEL \
			XCHAL_SEP	XCHAL_INT18_LEVEL \
			XCHAL_SEP	XCHAL_INT19_LEVEL \
			XCHAL_SEP	XCHAL_INT20_LEVEL \
			XCHAL_SEP	XCHAL_INT21_LEVEL \
			XCHAL_SEP	XCHAL_INT22_LEVEL \
			XCHAL_SEP	XCHAL_INT23_LEVEL \
			XCHAL_SEP	XCHAL_INT24_LEVEL \
			XCHAL_SEP	XCHAL_INT25_LEVEL \
			XCHAL_SEP	XCHAL_INT26_LEVEL \
			XCHAL_SEP	XCHAL_INT27_LEVEL \
			XCHAL_SEP	XCHAL_INT28_LEVEL \
			XCHAL_SEP	XCHAL_INT29_LEVEL \
			XCHAL_SEP	XCHAL_INT30_LEVEL \
			XCHAL_SEP	XCHAL_INT31_LEVEL \
			XCHAL_SEP	XCHAL_INT32_LEVEL \
			XCHAL_SEP	XCHAL_INT33_LEVEL \
			XCHAL_SEP	XCHAL_INT34_LEVEL \
			XCHAL_SEP	XCHAL_INT35_LEVEL \
			XCHAL_SEP	XCHAL_INT36_LEVEL \
			XCHAL_SEP	XCHAL_INT37_LEVEL \
			XCHAL_SEP	XCHAL_INT38_LEVEL \
			XCHAL_SEP	XCHAL_INT39_LEVEL \
			XCHAL_SEP	XCHAL_INT40_LEVEL \
			XCHAL_SEP	XCHAL_INT41_LEVEL \
			XCHAL_SEP	XCHAL_INT42_LEVEL \
			XCHAL_SEP	XCHAL_INT43_LEVEL \
			XCHAL_SEP	XCHAL_INT44_LEVEL \
			XCHAL_SEP	XCHAL_INT45_LEVEL \
			XCHAL_SEP	XCHAL_INT46_LEVEL \
			XCHAL_SEP	XCHAL_INT47_LEVEL \
			XCHAL_SEP	XCHAL_INT48_LEVEL \
			XCHAL_SEP	XCHAL_INT49_LEVEL \
			XCHAL_SEP	XCHAL_INT50_LEVEL \
			XCHAL_SEP	XCHAL_INT51_LEVEL \
			XCHAL_SEP	XCHAL_INT52_LEVEL \
			XCHAL_SEP	XCHAL_INT53_LEVEL \
			XCHAL_SEP	XCHAL_INT54_LEVEL \
			XCHAL_SEP	XCHAL_INT55_LEVEL \
			XCHAL_SEP	XCHAL_INT56_LEVEL \
			XCHAL_SEP	XCHAL_INT57_LEVEL \
			XCHAL_SEP	XCHAL_INT58_LEVEL \
			XCHAL_SEP	XCHAL_INT59_LEVEL \
			XCHAL_SEP	XCHAL_INT60_LEVEL \
			XCHAL_SEP	XCHAL_INT61_LEVEL \
			XCHAL_SEP	XCHAL_INT62_LEVEL \
			XCHAL_SEP	XCHAL_INT63_LEVEL \
			XCHAL_SEP	XCHAL_INT64_LEVEL \
			XCHAL_SEP	XCHAL_INT65_LEVEL \
			XCHAL_SEP	XCHAL_INT66_LEVEL \
			XCHAL_SEP	XCHAL_INT67_LEVEL \
			XCHAL_SEP	XCHAL_INT68_LEVEL \
			XCHAL_SEP	XCHAL_INT69_LEVEL \
			XCHAL_SEP	XCHAL_INT70_LEVEL \
			XCHAL_SEP	XCHAL_INT71_LEVEL \
			XCHAL_SEP	XCHAL_INT72_LEVEL \
			XCHAL_SEP	XCHAL_INT73_LEVEL \
			XCHAL_SEP	XCHAL_INT74_LEVEL \
			XCHAL_SEP	XCHAL_INT75_LEVEL \
			XCHAL_SEP	XCHAL_INT76_LEVEL \
			XCHAL_SEP	XCHAL_INT77_LEVEL \
			XCHAL_SEP	XCHAL_INT78_LEVEL \
			XCHAL_SEP	XCHAL_INT79_LEVEL \
			XCHAL_SEP	XCHAL_INT80_LEVEL \
			XCHAL_SEP	XCHAL_INT81_LEVEL \
			XCHAL_SEP	XCHAL_INT82_LEVEL \
			XCHAL_SEP	XCHAL_INT83_LEVEL \
			XCHAL_SEP	XCHAL_INT84_LEVEL \
			XCHAL_SEP	XCHAL_INT85_LEVEL \
			XCHAL_SEP	XCHAL_INT86_LEVEL \
			XCHAL_SEP	XCHAL_INT87_LEVEL \
			XCHAL_SEP	XCHAL_INT88_LEVEL \
			XCHAL_SEP	XCHAL_INT89_LEVEL \
			XCHAL_SEP	XCHAL_INT90_LEVEL \
			XCHAL_SEP	XCHAL_INT91_LEVEL \
			XCHAL_SEP	XCHAL_INT92_LEVEL \
			XCHAL_SEP	XCHAL_INT93_LEVEL \
			XCHAL_SEP	XCHAL_INT94_LEVEL \
			XCHAL_SEP	XCHAL_INT95_LEVEL \
			XCHAL_SEP	XCHAL_INT96_LEVEL \
			XCHAL_SEP	XCHAL_INT97_LEVEL \
			XCHAL_SEP	XCHAL_INT98_LEVEL \
			XCHAL_SEP	XCHAL_INT99_LEVEL \
			XCHAL_SEP	XCHAL_INT100_LEVEL \
			XCHAL_SEP	XCHAL_INT101_LEVEL \
			XCHAL_SEP	XCHAL_INT102_LEVEL \
			XCHAL_SEP	XCHAL_INT103_LEVEL \
			XCHAL_SEP	XCHAL_INT104_LEVEL \
			XCHAL_SEP	XCHAL_INT105_LEVEL \
			XCHAL_SEP	XCHAL_INT106_LEVEL \
			XCHAL_SEP	XCHAL_INT107_LEVEL \
			XCHAL_SEP	XCHAL_INT108_LEVEL \
			XCHAL_SEP	XCHAL_INT109_LEVEL \
			XCHAL_SEP	XCHAL_INT110_LEVEL \
			XCHAL_SEP	XCHAL_INT111_LEVEL \
			XCHAL_SEP	XCHAL_INT112_LEVEL \
			XCHAL_SEP	XCHAL_INT113_LEVEL \
			XCHAL_SEP	XCHAL_INT114_LEVEL \
			XCHAL_SEP	XCHAL_INT115_LEVEL \
			XCHAL_SEP	XCHAL_INT116_LEVEL \
			XCHAL_SEP	XCHAL_INT117_LEVEL \
			XCHAL_SEP	XCHAL_INT118_LEVEL \
			XCHAL_SEP	XCHAL_INT119_LEVEL \
			XCHAL_SEP	XCHAL_INT120_LEVEL \
			XCHAL_SEP	XCHAL_INT121_LEVEL \
			XCHAL_SEP	XCHAL_INT122_LEVEL \
			XCHAL_SEP	XCHAL_INT123_LEVEL \
			XCHAL_SEP	XCHAL_INT124_LEVEL \
			XCHAL_SEP	XCHAL_INT125_LEVEL \
			XCHAL_SEP	XCHAL_INT126_LEVEL \
			XCHAL_SEP	XCHAL_INT127_LEVEL

/*  Array of types of each possible interrupt:  */
#define XCHAL_INT_TYPES			XCHAL_INT0_TYPE \
			XCHAL_SEP	XCHAL_INT1_TYPE \
			XCHAL_SEP	XCHAL_INT2_TYPE \
			XCHAL_SEP	XCHAL_INT3_TYPE \
			XCHAL_SEP	XCHAL_INT4_TYPE \
			XCHAL_SEP	XCHAL_INT5_TYPE \
			XCHAL_SEP	XCHAL_INT6_TYPE \
			XCHAL_SEP	XCHAL_INT7_TYPE \
			XCHAL_SEP	XCHAL_INT8_TYPE \
			XCHAL_SEP	XCHAL_INT9_TYPE \
			XCHAL_SEP	XCHAL_INT10_TYPE \
			XCHAL_SEP	XCHAL_INT11_TYPE \
			XCHAL_SEP	XCHAL_INT12_TYPE \
			XCHAL_SEP	XCHAL_INT13_TYPE \
			XCHAL_SEP	XCHAL_INT14_TYPE \
			XCHAL_SEP	XCHAL_INT15_TYPE \
			XCHAL_SEP	XCHAL_INT16_TYPE \
			XCHAL_SEP	XCHAL_INT17_TYPE \
			XCHAL_SEP	XCHAL_INT18_TYPE \
			XCHAL_SEP	XCHAL_INT19_TYPE \
			XCHAL_SEP	XCHAL_INT20_TYPE \
			XCHAL_SEP	XCHAL_INT21_TYPE \
			XCHAL_SEP	XCHAL_INT22_TYPE \
			XCHAL_SEP	XCHAL_INT23_TYPE \
			XCHAL_SEP	XCHAL_INT24_TYPE \
			XCHAL_SEP	XCHAL_INT25_TYPE \
			XCHAL_SEP	XCHAL_INT26_TYPE \
			XCHAL_SEP	XCHAL_INT27_TYPE \
			XCHAL_SEP	XCHAL_INT28_TYPE \
			XCHAL_SEP	XCHAL_INT29_TYPE \
			XCHAL_SEP	XCHAL_INT30_TYPE \
			XCHAL_SEP	XCHAL_INT31_TYPE \
			XCHAL_SEP	XCHAL_INT32_TYPE \
			XCHAL_SEP	XCHAL_INT33_TYPE \
			XCHAL_SEP	XCHAL_INT34_TYPE \
			XCHAL_SEP	XCHAL_INT35_TYPE \
			XCHAL_SEP	XCHAL_INT36_TYPE \
			XCHAL_SEP	XCHAL_INT37_TYPE \
			XCHAL_SEP	XCHAL_INT38_TYPE \
			XCHAL_SEP	XCHAL_INT39_TYPE \
			XCHAL_SEP	XCHAL_INT40_TYPE \
			XCHAL_SEP	XCHAL_INT41_TYPE \
			XCHAL_SEP	XCHAL_INT42_TYPE \
			XCHAL_SEP	XCHAL_INT43_TYPE \
			XCHAL_SEP	XCHAL_INT44_TYPE \
			XCHAL_SEP	XCHAL_INT45_TYPE \
			XCHAL_SEP	XCHAL_INT46_TYPE \
			XCHAL_SEP	XCHAL_INT47_TYPE \
			XCHAL_SEP	XCHAL_INT48_TYPE \
			XCHAL_SEP	XCHAL_INT49_TYPE \
			XCHAL_SEP	XCHAL_INT50_TYPE \
			XCHAL_SEP	XCHAL_INT51_TYPE \
			XCHAL_SEP	XCHAL_INT52_TYPE \
			XCHAL_SEP	XCHAL_INT53_TYPE \
			XCHAL_SEP	XCHAL_INT54_TYPE \
			XCHAL_SEP	XCHAL_INT55_TYPE \
			XCHAL_SEP	XCHAL_INT56_TYPE \
			XCHAL_SEP	XCHAL_INT57_TYPE \
			XCHAL_SEP	XCHAL_INT58_TYPE \
			XCHAL_SEP	XCHAL_INT59_TYPE \
			XCHAL_SEP	XCHAL_INT60_TYPE \
			XCHAL_SEP	XCHAL_INT61_TYPE \
			XCHAL_SEP	XCHAL_INT62_TYPE \
			XCHAL_SEP	XCHAL_INT63_TYPE \
			XCHAL_SEP	XCHAL_INT64_TYPE \
			XCHAL_SEP	XCHAL_INT65_TYPE \
			XCHAL_SEP	XCHAL_INT66_TYPE \
			XCHAL_SEP	XCHAL_INT67_TYPE \
			XCHAL_SEP	XCHAL_INT68_TYPE \
			XCHAL_SEP	XCHAL_INT69_TYPE \
			XCHAL_SEP	XCHAL_INT70_TYPE \
			XCHAL_SEP	XCHAL_INT71_TYPE \
			XCHAL_SEP	XCHAL_INT72_TYPE \
			XCHAL_SEP	XCHAL_INT73_TYPE \
			XCHAL_SEP	XCHAL_INT74_TYPE \
			XCHAL_SEP	XCHAL_INT75_TYPE \
			XCHAL_SEP	XCHAL_INT76_TYPE \
			XCHAL_SEP	XCHAL_INT77_TYPE \
			XCHAL_SEP	XCHAL_INT78_TYPE \
			XCHAL_SEP	XCHAL_INT79_TYPE \
			XCHAL_SEP	XCHAL_INT80_TYPE \
			XCHAL_SEP	XCHAL_INT81_TYPE \
			XCHAL_SEP	XCHAL_INT82_TYPE \
			XCHAL_SEP	XCHAL_INT83_TYPE \
			XCHAL_SEP	XCHAL_INT84_TYPE \
			XCHAL_SEP	XCHAL_INT85_TYPE \
			XCHAL_SEP	XCHAL_INT86_TYPE \
			XCHAL_SEP	XCHAL_INT87_TYPE \
			XCHAL_SEP	XCHAL_INT88_TYPE \
			XCHAL_SEP	XCHAL_INT89_TYPE \
			XCHAL_SEP	XCHAL_INT90_TYPE \
			XCHAL_SEP	XCHAL_INT91_TYPE \
			XCHAL_SEP	XCHAL_INT92_TYPE \
			XCHAL_SEP	XCHAL_INT93_TYPE \
			XCHAL_SEP	XCHAL_INT94_TYPE \
			XCHAL_SEP	XCHAL_INT95_TYPE \
			XCHAL_SEP	XCHAL_INT96_TYPE \
			XCHAL_SEP	XCHAL_INT97_TYPE \
			XCHAL_SEP	XCHAL_INT98_TYPE \
			XCHAL_SEP	XCHAL_INT99_TYPE \
			XCHAL_SEP	XCHAL_INT100_TYPE \
			XCHAL_SEP	XCHAL_INT101_TYPE \
			XCHAL_SEP	XCHAL_INT102_TYPE \
			XCHAL_SEP	XCHAL_INT103_TYPE \
			XCHAL_SEP	XCHAL_INT104_TYPE \
			XCHAL_SEP	XCHAL_INT105_TYPE \
			XCHAL_SEP	XCHAL_INT106_TYPE \
			XCHAL_SEP	XCHAL_INT107_TYPE \
			XCHAL_SEP	XCHAL_INT108_TYPE \
			XCHAL_SEP	XCHAL_INT109_TYPE \
			XCHAL_SEP	XCHAL_INT110_TYPE \
			XCHAL_SEP	XCHAL_INT111_TYPE \
			XCHAL_SEP	XCHAL_INT112_TYPE \
			XCHAL_SEP	XCHAL_INT113_TYPE \
			XCHAL_SEP	XCHAL_INT114_TYPE \
			XCHAL_SEP	XCHAL_INT115_TYPE \
			XCHAL_SEP	XCHAL_INT116_TYPE \
			XCHAL_SEP	XCHAL_INT117_TYPE \
			XCHAL_SEP	XCHAL_INT118_TYPE \
			XCHAL_SEP	XCHAL_INT119_TYPE \
			XCHAL_SEP	XCHAL_INT120_TYPE \
			XCHAL_SEP	XCHAL_INT121_TYPE \
			XCHAL_SEP	XCHAL_INT122_TYPE \
			XCHAL_SEP	XCHAL_INT123_TYPE \
			XCHAL_SEP	XCHAL_INT124_TYPE \
			XCHAL_SEP	XCHAL_INT125_TYPE \
			XCHAL_SEP	XCHAL_INT126_TYPE \
			XCHAL_SEP	XCHAL_INT127_TYPE

/*  Array of masks of interrupts for each type of interrupt:  */
#define XCHAL_INTTYPE_MASKS		XCHAL_INTTYPE_MASK_UNCONFIGURED	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_SOFTWARE	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_EDGE	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_EXTERN_LEVEL	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_TIMER	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_NMI		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_WRITE_ERROR	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_IDMA_DONE	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_IDMA_ERR	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_GS_ERR	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK_L2_ERR
#if XCHAL_NUM_INTERRUPTS > 32
#define XCHAL_INTTYPE_MASKS1		XCHAL_INTTYPE_MASK1_UNCONFIGURED	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_SOFTWARE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_EXTERN_EDGE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_EXTERN_LEVEL	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_TIMER		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_NMI			\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_WRITE_ERROR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_IDMA_DONE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_IDMA_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_GS_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK1_L2_ERR
#define XCHAL_INTTYPE_MASKS2		XCHAL_INTTYPE_MASK2_UNCONFIGURED	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_SOFTWARE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_EXTERN_EDGE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_EXTERN_LEVEL	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_TIMER		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_NMI			\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_WRITE_ERROR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_IDMA_DONE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_IDMA_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_GS_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK2_L2_ERR
#define XCHAL_INTTYPE_MASKS3		XCHAL_INTTYPE_MASK3_UNCONFIGURED	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_SOFTWARE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_EXTERN_EDGE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_EXTERN_LEVEL	\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_TIMER		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_NMI			\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_WRITE_ERROR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_IDMA_DONE		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_IDMA_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_GS_ERR		\
			XCHAL_SEP	XCHAL_INTTYPE_MASK3_L2_ERR
#endif

/*  Interrupts that can be cleared using the INTCLEAR special register:  */
#define XCHAL_INTCLEARABLE_MASK		(XCHAL_INTTYPE_MASK_SOFTWARE+XCHAL_INTTYPE_MASK_EXTERN_EDGE+XCHAL_INTTYPE_MASK_WRITE_ERROR)
#if XCHAL_NUM_INTERRUPTS > 32
#define XCHAL_INTCLEARABLE_MASK1	(XCHAL_INTTYPE_MASK1_SOFTWARE+XCHAL_INTTYPE_MASK1_EXTERN_EDGE+XCHAL_INTTYPE_MASK1_WRITE_ERROR)
#define XCHAL_INTCLEARABLE_MASK2	(XCHAL_INTTYPE_MASK2_SOFTWARE+XCHAL_INTTYPE_MASK2_EXTERN_EDGE+XCHAL_INTTYPE_MASK2_WRITE_ERROR)
#define XCHAL_INTCLEARABLE_MASK3	(XCHAL_INTTYPE_MASK3_SOFTWARE+XCHAL_INTTYPE_MASK3_EXTERN_EDGE+XCHAL_INTTYPE_MASK3_WRITE_ERROR)
#endif

/*  Interrupts that can be triggered using the INTSET special register:  */
#define XCHAL_INTSETTABLE_MASK		XCHAL_INTTYPE_MASK_SOFTWARE
#if XCHAL_NUM_INTERRUPTS > 32
#define XCHAL_INTSETTABLE_MASK1		XCHAL_INTTYPE_MASK1_SOFTWARE
#define XCHAL_INTSETTABLE_MASK2		XCHAL_INTTYPE_MASK2_SOFTWARE
#define XCHAL_INTSETTABLE_MASK3		XCHAL_INTTYPE_MASK3_SOFTWARE
#endif


/*  For backward compatibility and for the array macros, define macros for
 *  each unconfigured interrupt number (unfortunately, the value of
 *  XTHAL_INTTYPE_UNCONFIGURED is not zero):  */
#if XCHAL_NUM_INTERRUPTS == 0
# define XCHAL_INT0_LEVEL		0
# define XCHAL_INT0_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 1
# define XCHAL_INT1_LEVEL		0
# define XCHAL_INT1_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 2
# define XCHAL_INT2_LEVEL		0
# define XCHAL_INT2_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 3
# define XCHAL_INT3_LEVEL		0
# define XCHAL_INT3_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 4
# define XCHAL_INT4_LEVEL		0
# define XCHAL_INT4_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 5
# define XCHAL_INT5_LEVEL		0
# define XCHAL_INT5_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 6
# define XCHAL_INT6_LEVEL		0
# define XCHAL_INT6_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 7
# define XCHAL_INT7_LEVEL		0
# define XCHAL_INT7_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 8
# define XCHAL_INT8_LEVEL		0
# define XCHAL_INT8_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 9
# define XCHAL_INT9_LEVEL		0
# define XCHAL_INT9_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 10
# define XCHAL_INT10_LEVEL		0
# define XCHAL_INT10_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 11
# define XCHAL_INT11_LEVEL		0
# define XCHAL_INT11_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 12
# define XCHAL_INT12_LEVEL		0
# define XCHAL_INT12_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 13
# define XCHAL_INT13_LEVEL		0
# define XCHAL_INT13_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 14
# define XCHAL_INT14_LEVEL		0
# define XCHAL_INT14_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 15
# define XCHAL_INT15_LEVEL		0
# define XCHAL_INT15_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 16
# define XCHAL_INT16_LEVEL		0
# define XCHAL_INT16_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 17
# define XCHAL_INT17_LEVEL		0
# define XCHAL_INT17_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 18
# define XCHAL_INT18_LEVEL		0
# define XCHAL_INT18_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 19
# define XCHAL_INT19_LEVEL		0
# define XCHAL_INT19_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 20
# define XCHAL_INT20_LEVEL		0
# define XCHAL_INT20_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 21
# define XCHAL_INT21_LEVEL		0
# define XCHAL_INT21_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 22
# define XCHAL_INT22_LEVEL		0
# define XCHAL_INT22_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 23
# define XCHAL_INT23_LEVEL		0
# define XCHAL_INT23_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 24
# define XCHAL_INT24_LEVEL		0
# define XCHAL_INT24_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 25
# define XCHAL_INT25_LEVEL		0
# define XCHAL_INT25_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 26
# define XCHAL_INT26_LEVEL		0
# define XCHAL_INT26_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 27
# define XCHAL_INT27_LEVEL		0
# define XCHAL_INT27_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 28
# define XCHAL_INT28_LEVEL		0
# define XCHAL_INT28_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 29
# define XCHAL_INT29_LEVEL		0
# define XCHAL_INT29_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 30
# define XCHAL_INT30_LEVEL		0
# define XCHAL_INT30_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 31
# define XCHAL_INT31_LEVEL		0
# define XCHAL_INT31_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 32
# define XCHAL_INT32_LEVEL		0
# define XCHAL_INT32_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 33
# define XCHAL_INT33_LEVEL		0
# define XCHAL_INT33_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 34
# define XCHAL_INT34_LEVEL		0
# define XCHAL_INT34_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 35
# define XCHAL_INT35_LEVEL		0
# define XCHAL_INT35_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 36
# define XCHAL_INT36_LEVEL		0
# define XCHAL_INT36_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 37
# define XCHAL_INT37_LEVEL		0
# define XCHAL_INT37_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 38
# define XCHAL_INT38_LEVEL		0
# define XCHAL_INT38_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 39
# define XCHAL_INT39_LEVEL		0
# define XCHAL_INT39_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 40
# define XCHAL_INT40_LEVEL		0
# define XCHAL_INT40_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 41
# define XCHAL_INT41_LEVEL		0
# define XCHAL_INT41_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 42
# define XCHAL_INT42_LEVEL		0
# define XCHAL_INT42_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 43
# define XCHAL_INT43_LEVEL		0
# define XCHAL_INT43_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 44
# define XCHAL_INT44_LEVEL		0
# define XCHAL_INT44_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 45
# define XCHAL_INT45_LEVEL		0
# define XCHAL_INT45_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 46
# define XCHAL_INT46_LEVEL		0
# define XCHAL_INT46_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 47
# define XCHAL_INT47_LEVEL		0
# define XCHAL_INT47_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 48
# define XCHAL_INT48_LEVEL		0
# define XCHAL_INT48_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 49
# define XCHAL_INT49_LEVEL		0
# define XCHAL_INT49_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 50
# define XCHAL_INT50_LEVEL		0
# define XCHAL_INT50_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 51
# define XCHAL_INT51_LEVEL		0
# define XCHAL_INT51_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 52
# define XCHAL_INT52_LEVEL		0
# define XCHAL_INT52_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 53
# define XCHAL_INT53_LEVEL		0
# define XCHAL_INT53_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 54
# define XCHAL_INT54_LEVEL		0
# define XCHAL_INT54_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 55
# define XCHAL_INT55_LEVEL		0
# define XCHAL_INT55_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 56
# define XCHAL_INT56_LEVEL		0
# define XCHAL_INT56_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 57
# define XCHAL_INT57_LEVEL		0
# define XCHAL_INT57_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 58
# define XCHAL_INT58_LEVEL		0
# define XCHAL_INT58_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 59
# define XCHAL_INT59_LEVEL		0
# define XCHAL_INT59_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 60
# define XCHAL_INT60_LEVEL		0
# define XCHAL_INT60_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 61
# define XCHAL_INT61_LEVEL		0
# define XCHAL_INT61_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 62
# define XCHAL_INT62_LEVEL		0
# define XCHAL_INT62_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 63
# define XCHAL_INT63_LEVEL		0
# define XCHAL_INT63_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 64
# define XCHAL_INT64_LEVEL		0
# define XCHAL_INT64_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 65
# define XCHAL_INT65_LEVEL		0
# define XCHAL_INT65_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 66
# define XCHAL_INT66_LEVEL		0
# define XCHAL_INT66_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 67
# define XCHAL_INT67_LEVEL		0
# define XCHAL_INT67_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 68
# define XCHAL_INT68_LEVEL		0
# define XCHAL_INT68_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 69
# define XCHAL_INT69_LEVEL		0
# define XCHAL_INT69_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 70
# define XCHAL_INT70_LEVEL		0
# define XCHAL_INT70_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 71
# define XCHAL_INT71_LEVEL		0
# define XCHAL_INT71_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 72
# define XCHAL_INT72_LEVEL		0
# define XCHAL_INT72_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 73
# define XCHAL_INT73_LEVEL		0
# define XCHAL_INT73_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 74
# define XCHAL_INT74_LEVEL		0
# define XCHAL_INT74_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 75
# define XCHAL_INT75_LEVEL		0
# define XCHAL_INT75_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 76
# define XCHAL_INT76_LEVEL		0
# define XCHAL_INT76_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 77
# define XCHAL_INT77_LEVEL		0
# define XCHAL_INT77_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 78
# define XCHAL_INT78_LEVEL		0
# define XCHAL_INT78_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 79
# define XCHAL_INT79_LEVEL		0
# define XCHAL_INT79_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 80
# define XCHAL_INT80_LEVEL		0
# define XCHAL_INT80_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 81
# define XCHAL_INT81_LEVEL		0
# define XCHAL_INT81_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 82
# define XCHAL_INT82_LEVEL		0
# define XCHAL_INT82_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 83
# define XCHAL_INT83_LEVEL		0
# define XCHAL_INT83_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 84
# define XCHAL_INT84_LEVEL		0
# define XCHAL_INT84_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 85
# define XCHAL_INT85_LEVEL		0
# define XCHAL_INT85_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 86
# define XCHAL_INT86_LEVEL		0
# define XCHAL_INT86_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 87
# define XCHAL_INT87_LEVEL		0
# define XCHAL_INT87_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 88
# define XCHAL_INT88_LEVEL		0
# define XCHAL_INT88_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 89
# define XCHAL_INT89_LEVEL		0
# define XCHAL_INT89_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 90
# define XCHAL_INT90_LEVEL		0
# define XCHAL_INT90_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 91
# define XCHAL_INT91_LEVEL		0
# define XCHAL_INT91_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 92
# define XCHAL_INT92_LEVEL		0
# define XCHAL_INT92_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 93
# define XCHAL_INT93_LEVEL		0
# define XCHAL_INT93_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 94
# define XCHAL_INT94_LEVEL		0
# define XCHAL_INT94_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 95
# define XCHAL_INT95_LEVEL		0
# define XCHAL_INT95_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 96
# define XCHAL_INT96_LEVEL		0
# define XCHAL_INT96_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 97
# define XCHAL_INT97_LEVEL		0
# define XCHAL_INT97_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 98
# define XCHAL_INT98_LEVEL		0
# define XCHAL_INT98_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 99
# define XCHAL_INT99_LEVEL		0
# define XCHAL_INT99_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 100
# define XCHAL_INT100_LEVEL		0
# define XCHAL_INT100_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 101
# define XCHAL_INT101_LEVEL		0
# define XCHAL_INT101_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 102
# define XCHAL_INT102_LEVEL		0
# define XCHAL_INT102_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 103
# define XCHAL_INT103_LEVEL		0
# define XCHAL_INT103_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 104
# define XCHAL_INT104_LEVEL		0
# define XCHAL_INT104_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 105
# define XCHAL_INT105_LEVEL		0
# define XCHAL_INT105_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 106
# define XCHAL_INT106_LEVEL		0
# define XCHAL_INT106_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 107
# define XCHAL_INT107_LEVEL		0
# define XCHAL_INT107_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 108
# define XCHAL_INT108_LEVEL		0
# define XCHAL_INT108_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 109
# define XCHAL_INT109_LEVEL		0
# define XCHAL_INT109_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 110
# define XCHAL_INT110_LEVEL		0
# define XCHAL_INT110_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 111
# define XCHAL_INT111_LEVEL		0
# define XCHAL_INT111_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 112
# define XCHAL_INT112_LEVEL		0
# define XCHAL_INT112_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 113
# define XCHAL_INT113_LEVEL		0
# define XCHAL_INT113_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 114
# define XCHAL_INT114_LEVEL		0
# define XCHAL_INT114_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 115
# define XCHAL_INT115_LEVEL		0
# define XCHAL_INT115_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 116
# define XCHAL_INT116_LEVEL		0
# define XCHAL_INT116_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 117
# define XCHAL_INT117_LEVEL		0
# define XCHAL_INT117_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 118
# define XCHAL_INT118_LEVEL		0
# define XCHAL_INT118_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 119
# define XCHAL_INT119_LEVEL		0
# define XCHAL_INT119_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 120
# define XCHAL_INT120_LEVEL		0
# define XCHAL_INT120_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 121
# define XCHAL_INT121_LEVEL		0
# define XCHAL_INT121_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 122
# define XCHAL_INT122_LEVEL		0
# define XCHAL_INT122_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 123
# define XCHAL_INT123_LEVEL		0
# define XCHAL_INT123_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 124
# define XCHAL_INT124_LEVEL		0
# define XCHAL_INT124_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 125
# define XCHAL_INT125_LEVEL		0
# define XCHAL_INT125_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 126
# define XCHAL_INT126_LEVEL		0
# define XCHAL_INT126_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif
#if XCHAL_NUM_INTERRUPTS <= 127
# define XCHAL_INT127_LEVEL		0
# define XCHAL_INT127_TYPE		XTHAL_INTTYPE_UNCONFIGURED
#endif


/*
 *  Masks and levels corresponding to each *external* interrupt.
 */

#define XCHAL_EXTINT0_MASK		(UINT32_C(1) << XCHAL_EXTINT0_NUM)
#define XCHAL_EXTINT0_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT0_NUM)
#define XCHAL_EXTINT1_MASK		(UINT32_C(1) << XCHAL_EXTINT1_NUM)
#define XCHAL_EXTINT1_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT1_NUM)
#define XCHAL_EXTINT2_MASK		(UINT32_C(1) << XCHAL_EXTINT2_NUM)
#define XCHAL_EXTINT2_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT2_NUM)
#define XCHAL_EXTINT3_MASK		(UINT32_C(1) << XCHAL_EXTINT3_NUM)
#define XCHAL_EXTINT3_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT3_NUM)
#define XCHAL_EXTINT4_MASK		(UINT32_C(1) << XCHAL_EXTINT4_NUM)
#define XCHAL_EXTINT4_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT4_NUM)
#define XCHAL_EXTINT5_MASK		(UINT32_C(1) << XCHAL_EXTINT5_NUM)
#define XCHAL_EXTINT5_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT5_NUM)
#define XCHAL_EXTINT6_MASK		(UINT32_C(1) << XCHAL_EXTINT6_NUM)
#define XCHAL_EXTINT6_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT6_NUM)
#define XCHAL_EXTINT7_MASK		(UINT32_C(1) << XCHAL_EXTINT7_NUM)
#define XCHAL_EXTINT7_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT7_NUM)
#define XCHAL_EXTINT8_MASK		(UINT32_C(1) << XCHAL_EXTINT8_NUM)
#define XCHAL_EXTINT8_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT8_NUM)
#define XCHAL_EXTINT9_MASK		(UINT32_C(1) << XCHAL_EXTINT9_NUM)
#define XCHAL_EXTINT9_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT9_NUM)
#define XCHAL_EXTINT10_MASK		(UINT32_C(1) << XCHAL_EXTINT10_NUM)
#define XCHAL_EXTINT10_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT10_NUM)
#define XCHAL_EXTINT11_MASK		(UINT32_C(1) << XCHAL_EXTINT11_NUM)
#define XCHAL_EXTINT11_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT11_NUM)
#define XCHAL_EXTINT12_MASK		(UINT32_C(1) << XCHAL_EXTINT12_NUM)
#define XCHAL_EXTINT12_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT12_NUM)
#define XCHAL_EXTINT13_MASK		(UINT32_C(1) << XCHAL_EXTINT13_NUM)
#define XCHAL_EXTINT13_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT13_NUM)
#define XCHAL_EXTINT14_MASK		(UINT32_C(1) << XCHAL_EXTINT14_NUM)
#define XCHAL_EXTINT14_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT14_NUM)
#define XCHAL_EXTINT15_MASK		(UINT32_C(1) << XCHAL_EXTINT15_NUM)
#define XCHAL_EXTINT15_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT15_NUM)
#define XCHAL_EXTINT16_MASK		(UINT32_C(1) << XCHAL_EXTINT16_NUM)
#define XCHAL_EXTINT16_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT16_NUM)
#define XCHAL_EXTINT17_MASK		(UINT32_C(1) << XCHAL_EXTINT17_NUM)
#define XCHAL_EXTINT17_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT17_NUM)
#define XCHAL_EXTINT18_MASK		(UINT32_C(1) << XCHAL_EXTINT18_NUM)
#define XCHAL_EXTINT18_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT18_NUM)
#define XCHAL_EXTINT19_MASK		(UINT32_C(1) << XCHAL_EXTINT19_NUM)
#define XCHAL_EXTINT19_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT19_NUM)
#define XCHAL_EXTINT20_MASK		(UINT32_C(1) << XCHAL_EXTINT20_NUM)
#define XCHAL_EXTINT20_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT20_NUM)
#define XCHAL_EXTINT21_MASK		(UINT32_C(1) << XCHAL_EXTINT21_NUM)
#define XCHAL_EXTINT21_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT21_NUM)
#define XCHAL_EXTINT22_MASK		(UINT32_C(1) << XCHAL_EXTINT22_NUM)
#define XCHAL_EXTINT22_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT22_NUM)
#define XCHAL_EXTINT23_MASK		(UINT32_C(1) << XCHAL_EXTINT23_NUM)
#define XCHAL_EXTINT23_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT23_NUM)
#define XCHAL_EXTINT24_MASK		(UINT32_C(1) << XCHAL_EXTINT24_NUM)
#define XCHAL_EXTINT24_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT24_NUM)
#define XCHAL_EXTINT25_MASK		(UINT32_C(1) << XCHAL_EXTINT25_NUM)
#define XCHAL_EXTINT25_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT25_NUM)
#define XCHAL_EXTINT26_MASK		(UINT32_C(1) << XCHAL_EXTINT26_NUM)
#define XCHAL_EXTINT26_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT26_NUM)
#define XCHAL_EXTINT27_MASK		(UINT32_C(1) << XCHAL_EXTINT27_NUM)
#define XCHAL_EXTINT27_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT27_NUM)
#define XCHAL_EXTINT28_MASK		(UINT32_C(1) << XCHAL_EXTINT28_NUM)
#define XCHAL_EXTINT28_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT28_NUM)
#define XCHAL_EXTINT29_MASK		(UINT32_C(1) << XCHAL_EXTINT29_NUM)
#define XCHAL_EXTINT29_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT29_NUM)
#define XCHAL_EXTINT30_MASK		(UINT32_C(1) << XCHAL_EXTINT30_NUM)
#define XCHAL_EXTINT30_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT30_NUM)
#define XCHAL_EXTINT31_MASK		(UINT32_C(1) << XCHAL_EXTINT31_NUM)
#define XCHAL_EXTINT31_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT31_NUM)
#define XCHAL_EXTINT32_MASK		(UINT32_C(1) << XCHAL_EXTINT32_NUM)
#define XCHAL_EXTINT32_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT32_NUM)
#define XCHAL_EXTINT33_MASK		(UINT32_C(1) << XCHAL_EXTINT33_NUM)
#define XCHAL_EXTINT33_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT33_NUM)
#define XCHAL_EXTINT34_MASK		(UINT32_C(1) << XCHAL_EXTINT34_NUM)
#define XCHAL_EXTINT34_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT34_NUM)
#define XCHAL_EXTINT35_MASK		(UINT32_C(1) << XCHAL_EXTINT35_NUM)
#define XCHAL_EXTINT35_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT35_NUM)
#define XCHAL_EXTINT36_MASK		(UINT32_C(1) << XCHAL_EXTINT36_NUM)
#define XCHAL_EXTINT36_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT36_NUM)
#define XCHAL_EXTINT37_MASK		(UINT32_C(1) << XCHAL_EXTINT37_NUM)
#define XCHAL_EXTINT37_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT37_NUM)
#define XCHAL_EXTINT38_MASK		(UINT32_C(1) << XCHAL_EXTINT38_NUM)
#define XCHAL_EXTINT38_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT38_NUM)
#define XCHAL_EXTINT39_MASK		(UINT32_C(1) << XCHAL_EXTINT39_NUM)
#define XCHAL_EXTINT39_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT39_NUM)
#define XCHAL_EXTINT40_MASK		(UINT32_C(1) << XCHAL_EXTINT40_NUM)
#define XCHAL_EXTINT40_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT40_NUM)
#define XCHAL_EXTINT41_MASK		(UINT32_C(1) << XCHAL_EXTINT41_NUM)
#define XCHAL_EXTINT41_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT41_NUM)
#define XCHAL_EXTINT42_MASK		(UINT32_C(1) << XCHAL_EXTINT42_NUM)
#define XCHAL_EXTINT42_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT42_NUM)
#define XCHAL_EXTINT43_MASK		(UINT32_C(1) << XCHAL_EXTINT43_NUM)
#define XCHAL_EXTINT43_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT43_NUM)
#define XCHAL_EXTINT44_MASK		(UINT32_C(1) << XCHAL_EXTINT44_NUM)
#define XCHAL_EXTINT44_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT44_NUM)
#define XCHAL_EXTINT45_MASK		(UINT32_C(1) << XCHAL_EXTINT45_NUM)
#define XCHAL_EXTINT45_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT45_NUM)
#define XCHAL_EXTINT46_MASK		(UINT32_C(1) << XCHAL_EXTINT46_NUM)
#define XCHAL_EXTINT46_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT46_NUM)
#define XCHAL_EXTINT47_MASK		(UINT32_C(1) << XCHAL_EXTINT47_NUM)
#define XCHAL_EXTINT47_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT47_NUM)
#define XCHAL_EXTINT48_MASK		(UINT32_C(1) << XCHAL_EXTINT48_NUM)
#define XCHAL_EXTINT48_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT48_NUM)
#define XCHAL_EXTINT49_MASK		(UINT32_C(1) << XCHAL_EXTINT49_NUM)
#define XCHAL_EXTINT49_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT49_NUM)
#define XCHAL_EXTINT50_MASK		(UINT32_C(1) << XCHAL_EXTINT50_NUM)
#define XCHAL_EXTINT50_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT50_NUM)
#define XCHAL_EXTINT51_MASK		(UINT32_C(1) << XCHAL_EXTINT51_NUM)
#define XCHAL_EXTINT51_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT51_NUM)
#define XCHAL_EXTINT52_MASK		(UINT32_C(1) << XCHAL_EXTINT52_NUM)
#define XCHAL_EXTINT52_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT52_NUM)
#define XCHAL_EXTINT53_MASK		(UINT32_C(1) << XCHAL_EXTINT53_NUM)
#define XCHAL_EXTINT53_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT53_NUM)
#define XCHAL_EXTINT54_MASK		(UINT32_C(1) << XCHAL_EXTINT54_NUM)
#define XCHAL_EXTINT54_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT54_NUM)
#define XCHAL_EXTINT55_MASK		(UINT32_C(1) << XCHAL_EXTINT55_NUM)
#define XCHAL_EXTINT55_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT55_NUM)
#define XCHAL_EXTINT56_MASK		(UINT32_C(1) << XCHAL_EXTINT56_NUM)
#define XCHAL_EXTINT56_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT56_NUM)
#define XCHAL_EXTINT57_MASK		(UINT32_C(1) << XCHAL_EXTINT57_NUM)
#define XCHAL_EXTINT57_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT57_NUM)
#define XCHAL_EXTINT58_MASK		(UINT32_C(1) << XCHAL_EXTINT58_NUM)
#define XCHAL_EXTINT58_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT58_NUM)
#define XCHAL_EXTINT59_MASK		(UINT32_C(1) << XCHAL_EXTINT59_NUM)
#define XCHAL_EXTINT59_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT59_NUM)
#define XCHAL_EXTINT60_MASK		(UINT32_C(1) << XCHAL_EXTINT60_NUM)
#define XCHAL_EXTINT60_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT60_NUM)
#define XCHAL_EXTINT61_MASK		(UINT32_C(1) << XCHAL_EXTINT61_NUM)
#define XCHAL_EXTINT61_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT61_NUM)
#define XCHAL_EXTINT62_MASK		(UINT32_C(1) << XCHAL_EXTINT62_NUM)
#define XCHAL_EXTINT62_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT62_NUM)
#define XCHAL_EXTINT63_MASK		(UINT32_C(1) << XCHAL_EXTINT63_NUM)
#define XCHAL_EXTINT63_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT63_NUM)
#define XCHAL_EXTINT64_MASK		(UINT32_C(1) << XCHAL_EXTINT64_NUM)
#define XCHAL_EXTINT64_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT64_NUM)
#define XCHAL_EXTINT65_MASK		(UINT32_C(1) << XCHAL_EXTINT65_NUM)
#define XCHAL_EXTINT65_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT65_NUM)
#define XCHAL_EXTINT66_MASK		(UINT32_C(1) << XCHAL_EXTINT66_NUM)
#define XCHAL_EXTINT66_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT66_NUM)
#define XCHAL_EXTINT67_MASK		(UINT32_C(1) << XCHAL_EXTINT67_NUM)
#define XCHAL_EXTINT67_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT67_NUM)
#define XCHAL_EXTINT68_MASK		(UINT32_C(1) << XCHAL_EXTINT68_NUM)
#define XCHAL_EXTINT68_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT68_NUM)
#define XCHAL_EXTINT69_MASK		(UINT32_C(1) << XCHAL_EXTINT69_NUM)
#define XCHAL_EXTINT69_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT69_NUM)
#define XCHAL_EXTINT70_MASK		(UINT32_C(1) << XCHAL_EXTINT70_NUM)
#define XCHAL_EXTINT70_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT70_NUM)
#define XCHAL_EXTINT71_MASK		(UINT32_C(1) << XCHAL_EXTINT71_NUM)
#define XCHAL_EXTINT71_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT71_NUM)
#define XCHAL_EXTINT72_MASK		(UINT32_C(1) << XCHAL_EXTINT72_NUM)
#define XCHAL_EXTINT72_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT72_NUM)
#define XCHAL_EXTINT73_MASK		(UINT32_C(1) << XCHAL_EXTINT73_NUM)
#define XCHAL_EXTINT73_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT73_NUM)
#define XCHAL_EXTINT74_MASK		(UINT32_C(1) << XCHAL_EXTINT74_NUM)
#define XCHAL_EXTINT74_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT74_NUM)
#define XCHAL_EXTINT75_MASK		(UINT32_C(1) << XCHAL_EXTINT75_NUM)
#define XCHAL_EXTINT75_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT75_NUM)
#define XCHAL_EXTINT76_MASK		(UINT32_C(1) << XCHAL_EXTINT76_NUM)
#define XCHAL_EXTINT76_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT76_NUM)
#define XCHAL_EXTINT77_MASK		(UINT32_C(1) << XCHAL_EXTINT77_NUM)
#define XCHAL_EXTINT77_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT77_NUM)
#define XCHAL_EXTINT78_MASK		(UINT32_C(1) << XCHAL_EXTINT78_NUM)
#define XCHAL_EXTINT78_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT78_NUM)
#define XCHAL_EXTINT79_MASK		(UINT32_C(1) << XCHAL_EXTINT79_NUM)
#define XCHAL_EXTINT79_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT79_NUM)
#define XCHAL_EXTINT80_MASK		(UINT32_C(1) << XCHAL_EXTINT80_NUM)
#define XCHAL_EXTINT80_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT80_NUM)
#define XCHAL_EXTINT81_MASK		(UINT32_C(1) << XCHAL_EXTINT81_NUM)
#define XCHAL_EXTINT81_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT81_NUM)
#define XCHAL_EXTINT82_MASK		(UINT32_C(1) << XCHAL_EXTINT82_NUM)
#define XCHAL_EXTINT82_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT82_NUM)
#define XCHAL_EXTINT83_MASK		(UINT32_C(1) << XCHAL_EXTINT83_NUM)
#define XCHAL_EXTINT83_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT83_NUM)
#define XCHAL_EXTINT84_MASK		(UINT32_C(1) << XCHAL_EXTINT84_NUM)
#define XCHAL_EXTINT84_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT84_NUM)
#define XCHAL_EXTINT85_MASK		(UINT32_C(1) << XCHAL_EXTINT85_NUM)
#define XCHAL_EXTINT85_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT85_NUM)
#define XCHAL_EXTINT86_MASK		(UINT32_C(1) << XCHAL_EXTINT86_NUM)
#define XCHAL_EXTINT86_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT86_NUM)
#define XCHAL_EXTINT87_MASK		(UINT32_C(1) << XCHAL_EXTINT87_NUM)
#define XCHAL_EXTINT87_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT87_NUM)
#define XCHAL_EXTINT88_MASK		(UINT32_C(1) << XCHAL_EXTINT88_NUM)
#define XCHAL_EXTINT88_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT88_NUM)
#define XCHAL_EXTINT89_MASK		(UINT32_C(1) << XCHAL_EXTINT89_NUM)
#define XCHAL_EXTINT89_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT89_NUM)
#define XCHAL_EXTINT90_MASK		(UINT32_C(1) << XCHAL_EXTINT90_NUM)
#define XCHAL_EXTINT90_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT90_NUM)
#define XCHAL_EXTINT91_MASK		(UINT32_C(1) << XCHAL_EXTINT91_NUM)
#define XCHAL_EXTINT91_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT91_NUM)
#define XCHAL_EXTINT92_MASK		(UINT32_C(1) << XCHAL_EXTINT92_NUM)
#define XCHAL_EXTINT92_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT92_NUM)
#define XCHAL_EXTINT93_MASK		(UINT32_C(1) << XCHAL_EXTINT93_NUM)
#define XCHAL_EXTINT93_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT93_NUM)
#define XCHAL_EXTINT94_MASK		(UINT32_C(1) << XCHAL_EXTINT94_NUM)
#define XCHAL_EXTINT94_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT94_NUM)
#define XCHAL_EXTINT95_MASK		(UINT32_C(1) << XCHAL_EXTINT95_NUM)
#define XCHAL_EXTINT95_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT95_NUM)
#define XCHAL_EXTINT96_MASK		(UINT32_C(1) << XCHAL_EXTINT96_NUM)
#define XCHAL_EXTINT96_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT96_NUM)
#define XCHAL_EXTINT97_MASK		(UINT32_C(1) << XCHAL_EXTINT97_NUM)
#define XCHAL_EXTINT97_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT97_NUM)
#define XCHAL_EXTINT98_MASK		(UINT32_C(1) << XCHAL_EXTINT98_NUM)
#define XCHAL_EXTINT98_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT98_NUM)
#define XCHAL_EXTINT99_MASK		(UINT32_C(1) << XCHAL_EXTINT99_NUM)
#define XCHAL_EXTINT99_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT99_NUM)
#define XCHAL_EXTINT100_MASK		(UINT32_C(1) << XCHAL_EXTINT100_NUM)
#define XCHAL_EXTINT100_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT100_NUM)
#define XCHAL_EXTINT101_MASK		(UINT32_C(1) << XCHAL_EXTINT101_NUM)
#define XCHAL_EXTINT101_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT101_NUM)
#define XCHAL_EXTINT102_MASK		(UINT32_C(1) << XCHAL_EXTINT102_NUM)
#define XCHAL_EXTINT102_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT102_NUM)
#define XCHAL_EXTINT103_MASK		(UINT32_C(1) << XCHAL_EXTINT103_NUM)
#define XCHAL_EXTINT103_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT103_NUM)
#define XCHAL_EXTINT104_MASK		(UINT32_C(1) << XCHAL_EXTINT104_NUM)
#define XCHAL_EXTINT104_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT104_NUM)
#define XCHAL_EXTINT105_MASK		(UINT32_C(1) << XCHAL_EXTINT105_NUM)
#define XCHAL_EXTINT105_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT105_NUM)
#define XCHAL_EXTINT106_MASK		(UINT32_C(1) << XCHAL_EXTINT106_NUM)
#define XCHAL_EXTINT106_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT106_NUM)
#define XCHAL_EXTINT107_MASK		(UINT32_C(1) << XCHAL_EXTINT107_NUM)
#define XCHAL_EXTINT107_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT107_NUM)
#define XCHAL_EXTINT108_MASK		(UINT32_C(1) << XCHAL_EXTINT108_NUM)
#define XCHAL_EXTINT108_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT108_NUM)
#define XCHAL_EXTINT109_MASK		(UINT32_C(1) << XCHAL_EXTINT109_NUM)
#define XCHAL_EXTINT109_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT109_NUM)
#define XCHAL_EXTINT110_MASK		(UINT32_C(1) << XCHAL_EXTINT110_NUM)
#define XCHAL_EXTINT110_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT110_NUM)
#define XCHAL_EXTINT111_MASK		(UINT32_C(1) << XCHAL_EXTINT111_NUM)
#define XCHAL_EXTINT111_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT111_NUM)
#define XCHAL_EXTINT112_MASK		(UINT32_C(1) << XCHAL_EXTINT112_NUM)
#define XCHAL_EXTINT112_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT112_NUM)
#define XCHAL_EXTINT113_MASK		(UINT32_C(1) << XCHAL_EXTINT113_NUM)
#define XCHAL_EXTINT113_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT113_NUM)
#define XCHAL_EXTINT114_MASK		(UINT32_C(1) << XCHAL_EXTINT114_NUM)
#define XCHAL_EXTINT114_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT114_NUM)
#define XCHAL_EXTINT115_MASK		(UINT32_C(1) << XCHAL_EXTINT115_NUM)
#define XCHAL_EXTINT115_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT115_NUM)
#define XCHAL_EXTINT116_MASK		(UINT32_C(1) << XCHAL_EXTINT116_NUM)
#define XCHAL_EXTINT116_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT116_NUM)
#define XCHAL_EXTINT117_MASK		(UINT32_C(1) << XCHAL_EXTINT117_NUM)
#define XCHAL_EXTINT117_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT117_NUM)
#define XCHAL_EXTINT118_MASK		(UINT32_C(1) << XCHAL_EXTINT118_NUM)
#define XCHAL_EXTINT118_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT118_NUM)
#define XCHAL_EXTINT119_MASK		(UINT32_C(1) << XCHAL_EXTINT119_NUM)
#define XCHAL_EXTINT119_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT119_NUM)
#define XCHAL_EXTINT120_MASK		(UINT32_C(1) << XCHAL_EXTINT120_NUM)
#define XCHAL_EXTINT120_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT120_NUM)
#define XCHAL_EXTINT121_MASK		(UINT32_C(1) << XCHAL_EXTINT121_NUM)
#define XCHAL_EXTINT121_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT121_NUM)
#define XCHAL_EXTINT122_MASK		(UINT32_C(1) << XCHAL_EXTINT122_NUM)
#define XCHAL_EXTINT122_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT122_NUM)
#define XCHAL_EXTINT123_MASK		(UINT32_C(1) << XCHAL_EXTINT123_NUM)
#define XCHAL_EXTINT123_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT123_NUM)
#define XCHAL_EXTINT124_MASK		(UINT32_C(1) << XCHAL_EXTINT124_NUM)
#define XCHAL_EXTINT124_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT124_NUM)
#define XCHAL_EXTINT125_MASK		(UINT32_C(1) << XCHAL_EXTINT125_NUM)
#define XCHAL_EXTINT125_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT125_NUM)
#define XCHAL_EXTINT126_MASK		(UINT32_C(1) << XCHAL_EXTINT126_NUM)
#define XCHAL_EXTINT126_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT126_NUM)
#define XCHAL_EXTINT127_MASK		(UINT32_C(1) << XCHAL_EXTINT127_NUM)
#define XCHAL_EXTINT127_LEVEL		XCHAL_INT_LEVEL(XCHAL_EXTINT127_NUM)

#endif /* XCHAL_HAVE_XEA2 */

/*  Array of interrupts assigned to each timer (CCOMPARE0 to CCOMPARE3):  */
#define XCHAL_TIMER_INTERRUPTS		XCHAL_TIMER0_INTERRUPT \
			XCHAL_SEP	XCHAL_TIMER1_INTERRUPT \
			XCHAL_SEP	XCHAL_TIMER2_INTERRUPT \
			XCHAL_SEP	XCHAL_TIMER3_INTERRUPT


/*----------------------------------------------------------------------
			EXCEPTIONS and VECTORS
  ----------------------------------------------------------------------*/

#if XCHAL_HAVE_XEA2

/*  For backward compatibility ONLY -- DO NOT USE (will be removed in future release):  */
#ifdef XCHAL_USER_VECTOR_VADDR
#define XCHAL_PROGRAMEXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
#define XCHAL_USEREXC_VECTOR_VADDR	XCHAL_USER_VECTOR_VADDR
#endif
#ifdef XCHAL_USER_VECTOR_PADDR
# define XCHAL_PROGRAMEXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
# define XCHAL_USEREXC_VECTOR_PADDR	XCHAL_USER_VECTOR_PADDR
#endif
#ifdef XCHAL_KERNEL_VECTOR_VADDR
# define XCHAL_STACKEDEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
# define XCHAL_KERNELEXC_VECTOR_VADDR	XCHAL_KERNEL_VECTOR_VADDR
#endif
#ifdef XCHAL_KERNEL_VECTOR_PADDR
# define XCHAL_STACKEDEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
# define XCHAL_KERNELEXC_VECTOR_PADDR	XCHAL_KERNEL_VECTOR_PADDR
#endif

/*  Indexing macros:  */
#define I_XCHAL_INTLEVEL_VECTOR_VADDR(n)	XCHAL_INTLEVEL ## n ## _VECTOR_VADDR	// PRQA S 0342 # suppress MISRA RULE-20.10 "Using the glue operator ##"
#define XCHAL_INTLEVEL_VECTOR_VADDR(n)		I_XCHAL_INTLEVEL_VECTOR_VADDR(n)	/* n = 0 .. 15 */

#endif /* XCHAL_HAVE_XEA2 */


/*----------------------------------------------------------------------
				DEPRECATED
	(but still used by RTOS ports etc.)
  ----------------------------------------------------------------------*/
/*  PS (special register number 230):  */
#define XCHAL_PS_VALIDMASK		0x00070F3F
#define XCHAL_PS_INTLEVEL_BITS		4
#define XCHAL_PS_INTLEVEL_NUM		16
#define XCHAL_PS_INTLEVEL_SHIFT		0
#define XCHAL_PS_INTLEVEL_MASK		0x0000000F
#define XCHAL_PS_EXCM_BITS		1
#define XCHAL_PS_EXCM_NUM		2
#define XCHAL_PS_EXCM_SHIFT		4
#define XCHAL_PS_EXCM_MASK		0x00000010
#define XCHAL_PS_UM_BITS		1
#define XCHAL_PS_UM_NUM			2
#define XCHAL_PS_UM_SHIFT		5
#define XCHAL_PS_UM_MASK		0x00000020
#define XCHAL_PS_RING_BITS		2
#define XCHAL_PS_RING_NUM		4
#define XCHAL_PS_RING_SHIFT		6
#define XCHAL_PS_RING_MASK		0x000000C0
#define XCHAL_PS_OWB_BITS		4
#define XCHAL_PS_OWB_NUM		16
#define XCHAL_PS_OWB_SHIFT		8
#define XCHAL_PS_OWB_MASK		0x00000F00
#define XCHAL_PS_CALLINC_BITS		2
#define XCHAL_PS_CALLINC_NUM		4
#define XCHAL_PS_CALLINC_SHIFT		16
#define XCHAL_PS_CALLINC_MASK		0x00030000
#define XCHAL_PS_WOE_BITS		1
#define XCHAL_PS_WOE_NUM		2
#define XCHAL_PS_WOE_SHIFT		18
#define XCHAL_PS_WOE_MASK		0x00040000


/*----------------------------------------------------------------------
				TIMERS
  ----------------------------------------------------------------------*/


/*----------------------------------------------------------------------
			INTERNAL I/D RAM/ROMs and XLMI
  ----------------------------------------------------------------------*/


/*----------------------------------------------------------------------
				CACHE
  ----------------------------------------------------------------------*/


/*  Default PREFCTL value to enable prefetch.  */
#if XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RE_2012_0
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x00044)	/* enabled, not aggressive */
#elif XCHAL_HW_MIN_VERSION < XTENSA_HWVERSION_RF_2014_0
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x01044)	/* + enable prefetch to L1 */
#elif ((XCHAL_PREFETCH_ENTRIES >= 16) && XCHAL_HAVE_CACHE_BLOCKOPS)
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x81044)	/* 12 entries for block ops */
#elif ((XCHAL_PREFETCH_ENTRIES >= 8) && XCHAL_HAVE_CACHE_BLOCKOPS)
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x51044)	/* 5 entries for block ops */
#else
#if XCHAL_HAVE_NX
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x03044)	/* DL1 and IL1 are always 1 on NX */
#else 
#define XCHAL_CACHE_PREFCTL_DEFAULT	UINT32_C(0x01044)	/* 0 entries for block ops */
#endif
#endif


/*  Max for both I-cache and D-cache (used for general alignment):  */
#if XCHAL_ICACHE_LINESIZE > XCHAL_DCACHE_LINESIZE
# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_ICACHE_LINEWIDTH
# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_ICACHE_LINESIZE
#else
# define XCHAL_CACHE_LINEWIDTH_MAX	XCHAL_DCACHE_LINEWIDTH
# define XCHAL_CACHE_LINESIZE_MAX	XCHAL_DCACHE_LINESIZE
#endif

#define XCHAL_ICACHE_SETSIZE		(UINT32_C(1) << XCHAL_ICACHE_SETWIDTH)
#define XCHAL_DCACHE_SETSIZE		(UINT32_C(1) << XCHAL_DCACHE_SETWIDTH)
/*  Max for both I and D caches (used for cache-coherency page alignment):  */
#if XCHAL_ICACHE_SETWIDTH > XCHAL_DCACHE_SETWIDTH
# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_ICACHE_SETWIDTH
# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_ICACHE_SETSIZE
#else
# define XCHAL_CACHE_SETWIDTH_MAX	XCHAL_DCACHE_SETWIDTH
# define XCHAL_CACHE_SETSIZE_MAX	XCHAL_DCACHE_SETSIZE
#endif

/*  Instruction cache tag bits:  */
#define XCHAL_ICACHE_TAG_V_SHIFT	0
#define XCHAL_ICACHE_TAG_V		0x1	/* valid bit */
#if XCHAL_ICACHE_WAYS > 1
# define XCHAL_ICACHE_TAG_F_SHIFT	1
# define XCHAL_ICACHE_TAG_F		0x2	/* fill (LRU) bit */
#else
# define XCHAL_ICACHE_TAG_F_SHIFT	0
# define XCHAL_ICACHE_TAG_F		0	/* no fill (LRU) bit */
#endif
#if XCHAL_ICACHE_LINE_LOCKABLE
# define XCHAL_ICACHE_TAG_L_SHIFT	(XCHAL_ICACHE_TAG_F_SHIFT+1)
# define XCHAL_ICACHE_TAG_L		(UINT32_C(1) << XCHAL_ICACHE_TAG_L_SHIFT)	/* lock bit */
#else
# define XCHAL_ICACHE_TAG_L_SHIFT	XCHAL_ICACHE_TAG_F_SHIFT
# define XCHAL_ICACHE_TAG_L		0	/* no lock bit */
#endif
/*  Data cache tag bits:  */
#define XCHAL_DCACHE_TAG_V_SHIFT	0
#define XCHAL_DCACHE_TAG_V		0x1	/* valid bit */
#if XCHAL_DCACHE_WAYS > 1
# define XCHAL_DCACHE_TAG_F_SHIFT	1
# define XCHAL_DCACHE_TAG_F		0x2	/* fill (LRU) bit */
#else
# define XCHAL_DCACHE_TAG_F_SHIFT	0
# define XCHAL_DCACHE_TAG_F		0	/* no fill (LRU) bit */
#endif
#if XCHAL_DCACHE_IS_WRITEBACK
# define XCHAL_DCACHE_TAG_D_SHIFT	(XCHAL_DCACHE_TAG_F_SHIFT+1)
# define XCHAL_DCACHE_TAG_D		(UINT32_C(1) << XCHAL_DCACHE_TAG_D_SHIFT)	/* dirty bit */
#else
# define XCHAL_DCACHE_TAG_D_SHIFT	XCHAL_DCACHE_TAG_F_SHIFT
# define XCHAL_DCACHE_TAG_D		0	/* no dirty bit */
#endif
#if XCHAL_DCACHE_LINE_LOCKABLE
# define XCHAL_DCACHE_TAG_L_SHIFT	(XCHAL_DCACHE_TAG_D_SHIFT+1)
# define XCHAL_DCACHE_TAG_L		(UINT32_C(1) << XCHAL_DCACHE_TAG_L_SHIFT)	/* lock bit */
#else
# define XCHAL_DCACHE_TAG_L_SHIFT	XCHAL_DCACHE_TAG_D_SHIFT
# define XCHAL_DCACHE_TAG_L		0	/* no lock bit */
#endif

#if XCHAL_HAVE_XEA5
/*  Assume MEMCTL is always present and useful */
#define XCHAL_USE_MEMCTL		1
#else
/*  Whether MEMCTL register has anything useful  */
#define XCHAL_USE_MEMCTL		(((XCHAL_LOOP_BUFFER_SIZE > 0)	||      \
					XCHAL_DCACHE_IS_COHERENT	||      \
					XCHAL_HAVE_BRANCH_PREDICTION	||      \
					XCHAL_HAVE_ICACHE_DYN_ENABLE	||      \
					XCHAL_HAVE_DCACHE_DYN_ENABLE)	&&      \
					(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RE_2012_0))
#endif

/*  Default MEMCTL values:  */
#if XCHAL_HAVE_XEA5
/* Init and enable all possible ways. Writing the max value will
   set the fields to the max allowable values. */
#define XCHAL_CACHE_MEMCTL_DEFAULT	UINT32_C(0x00FFFF00)
#else
#if XCHAL_HAVE_ICACHE_DYN_ENABLE || XCHAL_HAVE_DCACHE_DYN_ENABLE || XCHAL_HAVE_CME_DOWNGRADES
#define XCHAL_CACHE_MEMCTL_DEFAULT	UINT32_C(0xFFFFFF08)	/* init all possible ways */
#else
#define XCHAL_CACHE_MEMCTL_DEFAULT	UINT32_C(0x00000000)	/* nothing to do */
#endif
#endif

#if XCHAL_DCACHE_IS_COHERENT
#define XCHAL_MEMCTL_SNOOP_EN		UINT32_C(0x02)	/* enable snoop */
#else
#define XCHAL_MEMCTL_SNOOP_EN		UINT32_C(0x00)	/* don't enable snoop */
#endif

#if (XCHAL_LOOP_BUFFER_SIZE == 0) || XCHAL_ERRATUM_453
#define XCHAL_MEMCTL_L0IBUF_EN		UINT32_C(0x00)	/* no loop buffer or don't enable */
#else
#define XCHAL_MEMCTL_L0IBUF_EN		UINT32_C(0x01)	/* enable loop buffer */
#endif

#if XCHAL_HAVE_BRANCH_PREDICTION
#define XCHAL_MEMCTL_BP_EN		UINT32_C(0x08)	/* enable branch prediction */
#else
#define XCHAL_MEMCTL_BP_EN		UINT32_C(0x00)	/* don't enable BP */
#endif

#define XCHAL_MEMCTL_DEFAULT		XCHAL_CACHE_MEMCTL_DEFAULT
#define XCHAL_MEMCTL_DEFAULT_POST	(XCHAL_MEMCTL_SNOOP_EN | XCHAL_MEMCTL_L0IBUF_EN | XCHAL_MEMCTL_BP_EN)


/*----------------------------------------------------------------------
				MMU
  ----------------------------------------------------------------------*/

/*  See <xtensa/config/core-matmap.h> for more details.  */

/*  Indexing macros:  */
// PRQA S 0342 ++ # begin-suppress MISRA RULE-20.10 "Using the glue operator ##"
#define I_XCHAL_ITLB_SET(n,_what)	XCHAL_ITLB_SET ## n ## _what
#define XCHAL_ITLB_SET(n,what)		I_XCHAL_ITLB_SET(n, _ ## what )
#define I_XCHAL_ITLB_SET_E(n,i,_what)	XCHAL_ITLB_SET ## n ## _E ## i ## _what
#define XCHAL_ITLB_SET_E(n,i,what)	I_XCHAL_ITLB_SET_E(n,i, _ ## what )
#define I_XCHAL_DTLB_SET(n,_what)	XCHAL_DTLB_SET ## n ## _what
#define XCHAL_DTLB_SET(n,what)		I_XCHAL_DTLB_SET(n, _ ## what )
#define I_XCHAL_DTLB_SET_E(n,i,_what)	XCHAL_DTLB_SET ## n ## _E ## i ## _what
#define XCHAL_DTLB_SET_E(n,i,what)	I_XCHAL_DTLB_SET_E(n,i, _ ## what )
// PRQA S 0342 -- # end-suppress MISRA RULE-20.10 "Using the glue operator ##"
/*
 *  Example use:  XCHAL_ITLB_SET(XCHAL_ITLB_ARF_SET0,ENTRIES)
 *	to get the value of XCHAL_ITLB_SET<n>_ENTRIES where <n> is the first auto-refill set.
 */

/*  Number of entries per autorefill way:  */
#define XCHAL_ITLB_ARF_ENTRIES		(UINT32_C(1) << XCHAL_ITLB_ARF_ENTRIES_LOG2)
#define XCHAL_DTLB_ARF_ENTRIES		(UINT32_C(1) << XCHAL_DTLB_ARF_ENTRIES_LOG2)

/*
 *  For full MMUs, report kernel RAM segment and kernel I/O segment static page mappings:
 */
#if XCHAL_HAVE_PTP_MMU && !XCHAL_HAVE_SPANNING_WAY
#define XCHAL_KSEG_CACHED_VADDR		UINT32_C(0xD0000000)	/* virt.addr of kernel RAM cached static map */
#define XCHAL_KSEG_CACHED_PADDR		UINT32_C(0x00000000)	/* phys.addr of kseg_cached */
#define XCHAL_KSEG_CACHED_SIZE		UINT32_C(0x08000000)	/* size in bytes of kseg_cached (assumed power of 2!!!) */
#define XCHAL_KSEG_BYPASS_VADDR		UINT32_C(0xD8000000)	/* virt.addr of kernel RAM bypass (uncached) static map */
#define XCHAL_KSEG_BYPASS_PADDR		UINT32_C(0x00000000)	/* phys.addr of kseg_bypass */
#define XCHAL_KSEG_BYPASS_SIZE		UINT32_C(0x08000000)	/* size in bytes of kseg_bypass (assumed power of 2!!!) */

#define XCHAL_KIO_CACHED_VADDR		UINT32_C(0xE0000000)	/* virt.addr of kernel I/O cached static map */
#define XCHAL_KIO_CACHED_PADDR		UINT32_C(0xF0000000)	/* phys.addr of kio_cached */
#define XCHAL_KIO_CACHED_SIZE		UINT32_C(0x10000000)	/* size in bytes of kio_cached (assumed power of 2!!!) */
#define XCHAL_KIO_BYPASS_VADDR		UINT32_C(0xF0000000)	/* virt.addr of kernel I/O bypass (uncached) static map */
#define XCHAL_KIO_BYPASS_PADDR		UINT32_C(0xF0000000)	/* phys.addr of kio_bypass */
#define XCHAL_KIO_BYPASS_SIZE		UINT32_C(0x10000000)	/* size in bytes of kio_bypass (assumed power of 2!!!) */

#define XCHAL_SEG_MAPPABLE_VADDR	UINT32_C(0x00000000)	/* start of largest non-static-mapped virtual addr area */
#define XCHAL_SEG_MAPPABLE_SIZE		UINT32_C(0xD0000000)	/* size in bytes of  "  */
/* define XCHAL_SEG_MAPPABLE2_xxx if more areas present, sorted in order of descending size.  */
#endif


#if XCHAL_HAVE_MPU && XCHAL_HAVE_LX && XCHAL_HAVE_XEA2
#define XCHAL_HAVE_CACHEADRDIS		1		/* CACHEADRDIS register present */
#else
#define XCHAL_HAVE_CACHEADRDIS		0
#endif

#if XCHAL_HAVE_APB && XCHAL_HAVE_XEA3 && defined(XTENSA_HWVERSION_NX1_1_1) && \
    (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_NX1_1_1)
#define XCHAL_HAVE_PROGRAMMABLE_APB	1
#else
#define XCHAL_HAVE_PROGRAMMABLE_APB	0
#endif


#if XCHAL_HAVE_MPU && defined(XTENSA_HWVERSION_RI_2020_5) && \
    (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RI_2020_5)
#define XCHAL_HAVE_MPU_EXECUTE_ONLY	1
#else
#define XCHAL_HAVE_MPU_EXECUTE_ONLY	0
#endif

#if defined(XTENSA_HWVERSION_RI_2020_5) && \
    (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RI_2020_5) && \
    XCHAL_HAVE_VECBASE
#define XCHAL_VECBASE_LOCK		1
#else
#define XCHAL_VECBASE_LOCK		0
#endif

/*----------------------------------------------------------------------
				MISC
  ----------------------------------------------------------------------*/

/*  Data alignment required if used for instructions:  */
#if XCHAL_INST_FETCH_WIDTH > XCHAL_DATA_WIDTH
# define XCHAL_ALIGN_MAX		XCHAL_INST_FETCH_WIDTH
#else
# define XCHAL_ALIGN_MAX		XCHAL_DATA_WIDTH
#endif

/*
 *  Names kept for backward compatibility.
 *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
 *   under which they are released.  In the T10##.# era there was no distinction.)
 */
#define XCHAL_HW_RELEASE_MAJOR		XCHAL_HW_VERSION_MAJOR
#define XCHAL_HW_RELEASE_MINOR		XCHAL_HW_VERSION_MINOR
#define XCHAL_HW_RELEASE_NAME		XCHAL_HW_VERSION_NAME

/*  The condition for the existence of the ATOMCTL register. */
#define XCHAL_HAVE_ATOMCTL		(XCHAL_HAVE_EXCLUSIVE || \
					(XCHAL_HAVE_S32C1I    && \
					(XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)))


/*----------------------------------------------------------------------
			COPROCESSORS and EXTRA STATE
  ----------------------------------------------------------------------*/

#define XCHAL_EXTRA_SA_SIZE		XCHAL_NCP_SA_SIZE
#define XCHAL_EXTRA_SA_ALIGN		XCHAL_NCP_SA_ALIGN
#define XCHAL_CPEXTRA_SA_SIZE		XCHAL_TOTAL_SA_SIZE
#define XCHAL_CPEXTRA_SA_ALIGN		XCHAL_TOTAL_SA_ALIGN

#if defined (_ASMLANGUAGE) || defined (__ASSEMBLER__)

	/*  Invoked at start of save area load/store sequence macro to setup macro
	 *  internal offsets.  Not usually invoked directly.
	 *	continue	0 for 1st sequence, 1 for subsequent consecutive ones.
	 *	totofs		offset from original ptr to next load/store location.
	 */
	.macro	xchal_sa_start	continue totofs
	.ifeq \continue
	 .set	.Lxchal_pofs_, 0	/* offset from original ptr to current \ptr */
	 .set	.Lxchal_ofs_, 0		/* offset from current \ptr to next load/store location */
	.endif
	.if \totofs + 1			/* if totofs specified (not -1) */
	 .set	.Lxchal_ofs_, \totofs - .Lxchal_pofs_	/* specific offset from original ptr */
	.endif
	.endm

	/*  Align portion of save area and bring ptr in range if necessary.
	 *  Used by save area load/store sequences.  Not usually invoked directly.
	 *  Allows combining multiple (sub-)sequences arbitrarily.
	 *	ptr		pointer to save area (may be off, see .Lxchal_pofs_)
	 *	minofs,maxofs	range of offset from cur ptr to next load/store loc;
	 *			minofs <= 0 <= maxofs  (0 must always be valid offset)
	 *			range must be within +/- 30kB or so.
	 *	ofsalign	alignment granularity of minofs .. maxofs (pow of 2)
	 *			(restriction on offset from ptr to next load/store loc)
	 *	totalign	align from orig ptr to next load/store loc (pow of 2)
	 */
	.macro	xchal_sa_align	ptr minofs maxofs ofsalign totalign
	/*  First align where we start accessing the next register
	 *  per \totalign relative to original ptr (i.e. start of the save area):
	 */
	.set	.Lxchal_ofs_, ((.Lxchal_pofs_ + .Lxchal_ofs_ + \totalign - 1) & -\totalign) - .Lxchal_pofs_
	/*  If necessary, adjust \ptr to bring .Lxchal_ofs_ in acceptable range:  */
	.if (((\maxofs) - .Lxchal_ofs_) & 0xC0000000) | ((.Lxchal_ofs_ - (\minofs)) & 0xC0000000) | (.Lxchal_ofs_ & (\ofsalign-1))
	 .set	.Ligmask, 0xFFFFFFFF
	 addi	\ptr, \ptr, (.Lxchal_ofs_ & .Ligmask)
	 .set	.Lxchal_pofs_, .Lxchal_pofs_ + (.Lxchal_ofs_ & .Ligmask)
	 .set	.Lxchal_ofs_, (.Lxchal_ofs_ & ~.Ligmask)
	.endif
	.endm
	/*
	 *  We could optimize for addi to expand to only addmi instead of
	 *  "addmi;addi", where possible.  Here's a partial example how:
	 * .set	.Lmaxmask, -(\ofsalign) & -(\totalign)
	 * .if (((\maxofs) + ~.Lmaxmask + 1) & 0xFFFFFF00) && ((.Lxchal_ofs_ & ~.Lmaxmask) == 0)
	 *  .set	.Ligmask, 0xFFFFFF00
	 * .elif ... ditto for negative ofs range ...
	 *  .set .Ligmask, 0xFFFFFF00
	 *  .set ... adjust per offset ...
	 * .else
	 *  .set .Ligmask, 0xFFFFFFFF
	 * .endif
	 */

	/*  Invoke this after xchal_XXX_{load,store} macros to restore \ptr.  */
	.macro	xchal_sa_ptr_restore	ptr
	.if .Lxchal_pofs_
	 addi	\ptr, \ptr, - .Lxchal_pofs_
	 .set	.Lxchal_ofs_, .Lxchal_ofs_ + .Lxchal_pofs_
	 .set	.Lxchal_pofs_, 0
	.endif
	.endm

	/*
	 *  Use as eg:
	 *	xchal_atmps_store a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
	 *	xchal_ncp_load a2, a0,a3,a4,a5
	 *	xchal_atmps_load  a1, SOMEOFS, XCHAL_SA_NUM_ATMPS, a4, a5
	 *
	 *  Specify only the ARs you *haven't* saved/restored already, up to 4.
	 *  They *must* be the *last* ARs (in same order) specified to save area
	 *  load/store sequences.  In the example above, a0 and a3 were already
	 *  saved/restored and unused (thus available) but a4 and a5 were not.
	 */
#define xchal_atmps_store	xchal_atmps_loadstore s32i,
#define xchal_atmps_load	xchal_atmps_loadstore l32i,
	.macro	xchal_atmps_loadstore	inst ptr offset nreq aa=0 ab=0 ac=0 ad=0
	.set	.Lnsaved_, 0
	.irp	reg,\aa,\ab,\ac,\ad
	 .ifeq 0x\reg ; .set .Lnsaved_,.Lnsaved_+1 ; .endif
	.endr
	.set	.Laofs_, 0
	.irp	reg,\aa,\ab,\ac,\ad
	 .ifgt (\nreq)-.Lnsaved_
	  \inst	\reg, \ptr, .Laofs_+\offset
	  .set	.Laofs_,.Laofs_+4
	  .set	.Lnsaved_,.Lnsaved_+1
	 .endif
	.endr
	.endm

	/*
	 * Argument and scratch registers for CP/NCP load/store macros.
	 */
#if defined (__riscv)
#define xchal_cpls_args		a0, t1, t2, t3, t4
#else
#define xchal_cpls_args		a2, a3, a4, a5, a6
#endif

#define xchal_extratie_load		xchal_ncptie_load
#define xchal_extratie_store		xchal_ncptie_store
#define xchal_extratie_load_args	xchal_ncptie_load  xchal_cpls_args
#define xchal_extratie_store_args	xchal_ncptie_store xchal_cpls_args
#define xchal_extra_load		xchal_ncp_load
#define xchal_extra_store		xchal_ncp_store
#define xchal_extra_load_args		xchal_ncp_load  
#define xchal_extra_store_args		xchal_ncp_store    xchal_cpls_args
#define xchal_extra_load_funcbody	xchal_ncp_load     xchal_cpls_args
#define xchal_extra_store_funcbody	xchal_ncp_store    xchal_cpls_args
#define xchal_cp0_store_args		xchal_cp0_store    xchal_cpls_args
#define xchal_cp0_load_args		xchal_cp0_load     xchal_cpls_args
#define xchal_cp1_store_args		xchal_cp1_store    xchal_cpls_args
#define xchal_cp1_load_args		xchal_cp1_load     xchal_cpls_args
#define xchal_cp2_store_args		xchal_cp2_store    xchal_cpls_args
#define xchal_cp2_load_args		xchal_cp2_load     xchal_cpls_args
#define xchal_cp3_store_args		xchal_cp3_store    xchal_cpls_args
#define xchal_cp3_load_args		xchal_cp3_load     xchal_cpls_args
#define xchal_cp4_store_args		xchal_cp4_store    xchal_cpls_args
#define xchal_cp4_load_args		xchal_cp4_load     xchal_cpls_args
#define xchal_cp5_store_args		xchal_cp5_store    xchal_cpls_args
#define xchal_cp5_load_args		xchal_cp5_load     xchal_cpls_args
#define xchal_cp6_store_args		xchal_cp6_store    xchal_cpls_args
#define xchal_cp6_load_args		xchal_cp6_load     xchal_cpls_args
#define xchal_cp7_store_args		xchal_cp7_store    xchal_cpls_args
#define xchal_cp7_load_args		xchal_cp7_load     xchal_cpls_args

/*  Defines for backward compatibility  */
#if !defined (__riscv)
#define xchal_extratie_load_a2		xchal_extratie_load_args
#define xchal_extratie_store_a2		xchal_extratie_store_args
#define xchal_extra_load_a2		xchal_extra_load_args
#define xchal_extra_store_a2		xchal_extra_store_args
#define xchal_cp0_store_a2		xchal_cp0_store_args
#define xchal_cp0_load_a2		xchal_cp0_load_args
#define xchal_cp1_store_a2		xchal_cp1_store_args
#define xchal_cp1_load_a2		xchal_cp1_load_args
#define xchal_cp2_store_a2		xchal_cp2_store_args
#define xchal_cp2_load_a2		xchal_cp2_load_args
#define xchal_cp3_store_a2		xchal_cp3_store_args
#define xchal_cp3_load_a2		xchal_cp3_load_args
#define xchal_cp4_store_a2		xchal_cp4_store_args
#define xchal_cp4_load_a2		xchal_cp4_load_args
#define xchal_cp5_store_a2		xchal_cp5_store_args
#define xchal_cp5_load_a2		xchal_cp5_load_args
#define xchal_cp6_store_a2		xchal_cp6_store_args
#define xchal_cp6_load_a2		xchal_cp6_load_args
#define xchal_cp7_store_a2		xchal_cp7_store_args
#define xchal_cp7_load_a2		xchal_cp7_load_args
#endif

/*  Empty placeholder macros for undefined coprocessors:  */
#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK) == 0
# if XCHAL_CP0_SA_SIZE == 0
	.macro xchal_cp0_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp0_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP1_SA_SIZE == 0
	.macro xchal_cp1_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp1_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP2_SA_SIZE == 0
	.macro xchal_cp2_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp2_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP3_SA_SIZE == 0
	.macro xchal_cp3_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp3_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP4_SA_SIZE == 0
	.macro xchal_cp4_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp4_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP5_SA_SIZE == 0
	.macro xchal_cp5_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp5_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP6_SA_SIZE == 0
	.macro xchal_cp6_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp6_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
# if XCHAL_CP7_SA_SIZE == 0
	.macro xchal_cp7_store	p a b c d continue=0 ofs=-1 select=-1 ; .endm
	.macro xchal_cp7_load	p a b c d continue=0 ofs=-1 select=-1 ; .endm
# endif
#endif

	/********************
	 *  Macros to create functions that save and restore the state of *any* TIE
	 *  coprocessor (by dynamic index).
	 */


	.macro	check_id id
#if defined (__riscv)
	li	t1, \id
	bne	a1, t1, 99f
#else
	bnei	a3, \id, 99f
#endif
	.endm

	/*
	 *  Macro that expands to the body of a function
	 *  that stores the selected coprocessor's state (registers etc).
	 *	Entry:	a2 = ptr to save area in which to save cp state
	 *		a3 = coprocessor number
	 *		(a0 and a1 for risc-v)
	 *	Exit:	any (caller-saved/temp) register may have been clobbered.
	 */
	.macro	xchal_cpi_store_funcbody
#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
# if XCHAL_CP0_SA_SIZE
	check_id 0
	xchal_cp0_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP1_SA_SIZE
	check_id 1
	xchal_cp1_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP2_SA_SIZE
	check_id 2
	xchal_cp2_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP3_SA_SIZE
	check_id 3
	xchal_cp3_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP4_SA_SIZE
	check_id 4
	xchal_cp4_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP5_SA_SIZE
	check_id 5
	xchal_cp5_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP6_SA_SIZE
	check_id 6
	xchal_cp6_store_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP7_SA_SIZE
	check_id 7
	xchal_cp7_store_args
99:
# endif
90:
#endif
	.endm

	/*
	 *  Macro that expands to the body of a function
	 *  that loads the selected coprocessor's state (registers etc).
	 *	Entry:	a2 = ptr to save area from which to restore cp state
	 *		a3 = coprocessor number
	 *	Exit:	any register a2-a15 (?) may have been clobbered.
	 */
	.macro	xchal_cpi_load_funcbody
#if (XCHAL_CP_MASK & ~XCHAL_CP_PORT_MASK)
# if XCHAL_CP0_SA_SIZE
	check_id 0
	xchal_cp0_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP1_SA_SIZE
	check_id 1
	xchal_cp1_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP2_SA_SIZE
	check_id 2
	xchal_cp2_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP3_SA_SIZE
	check_id 3
	xchal_cp3_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP4_SA_SIZE
	check_id 4
	xchal_cp4_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP5_SA_SIZE
	check_id 5
	xchal_cp5_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP6_SA_SIZE
	check_id 6
	xchal_cp6_load_args
#  if (XCHAL_CP_NUM > 1)
	j	90f
#  endif
99:
# endif
# if XCHAL_CP7_SA_SIZE
	check_id 7
	xchal_cp7_load_args
99:
# endif
90:
#endif
	.endm

#endif /*_ASMLANGUAGE or __ASSEMBLER__*/


/*  Other default macros for undefined coprocessors:  */
#ifndef XCHAL_CP0_NAME
# define XCHAL_CP0_NAME				NULL
# define XCHAL_CP0_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP0_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP1_NAME
# define XCHAL_CP1_NAME				NULL
# define XCHAL_CP1_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP1_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP2_NAME
# define XCHAL_CP2_NAME				NULL
# define XCHAL_CP2_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP2_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP3_NAME
# define XCHAL_CP3_NAME				NULL
# define XCHAL_CP3_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP3_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP4_NAME
# define XCHAL_CP4_NAME				NULL
# define XCHAL_CP4_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP4_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP5_NAME
# define XCHAL_CP5_NAME				NULL
# define XCHAL_CP5_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP5_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP6_NAME
# define XCHAL_CP6_NAME				NULL
# define XCHAL_CP6_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP6_SA_CONTENTS_LIBDB		/* empty */
#endif
#ifndef XCHAL_CP7_NAME
# define XCHAL_CP7_NAME				NULL
# define XCHAL_CP7_SA_CONTENTS_LIBDB_NUM	0
# define XCHAL_CP7_SA_CONTENTS_LIBDB		/* empty */
#endif

#if XCHAL_CP_MASK == 0
/*  Filler info for unassigned coprocessors, to simplify arrays etc:  */
#define XCHAL_CP0_SA_SIZE               UINT32_C(0)
#define XCHAL_CP0_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP1_SA_SIZE               UINT32_C(0)
#define XCHAL_CP1_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP2_SA_SIZE               UINT32_C(0)
#define XCHAL_CP2_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP3_SA_SIZE               UINT32_C(0)
#define XCHAL_CP3_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP4_SA_SIZE               UINT32_C(0)
#define XCHAL_CP4_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP5_SA_SIZE               UINT32_C(0)
#define XCHAL_CP5_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP6_SA_SIZE               UINT32_C(0)
#define XCHAL_CP6_SA_ALIGN              UINT32_C(1)
#define XCHAL_CP7_SA_SIZE               UINT32_C(0)
#define XCHAL_CP7_SA_ALIGN              UINT32_C(1)
#endif


/*  Indexing macros:  */
// PRQA S 0342 ++ # begin-suppress MISRA RULE-20.10 "Using the glue operator ##"
#define I_XCHAL_CP_SA_SIZE(n)		XCHAL_CP ## n ## _SA_SIZE
#define XCHAL_CP_SA_SIZE(n)		I_XCHAL_CP_SA_SIZE(n)	/* n = 0 .. 7 */
#define I_XCHAL_CP_SA_ALIGN(n)		XCHAL_CP ## n ## _SA_ALIGN
#define XCHAL_CP_SA_ALIGN(n)		I_XCHAL_CP_SA_ALIGN(n)	/* n = 0 .. 7 */
// PRQA S 0342 -- # end-suppress MISRA RULE-20.10 "Using the glue operator ##"

/*  Link-time HAL global variables that report coprocessor numbers by name
    (names are case-preserved from the original TIE):  */
#if !defined(_ASMLANGUAGE) && !defined(_NOCLANGUAGE) && !defined(__ASSEMBLER__)
# define I_XCJOIN(a,b)	a ## b		// PRQA S 0342 # suppress MISRA RULE-20.10 "Using the glue operator ##"
# define XCJOIN(a,b)	I_XCJOIN(a,b)	

# ifdef XCHAL_CP0_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP0_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP0_IDENT);
# endif
# ifdef XCHAL_CP1_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP1_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP1_IDENT);
# endif
# ifdef XCHAL_CP2_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP2_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP2_IDENT);
# endif
# ifdef XCHAL_CP3_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP3_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP3_IDENT);
# endif
# ifdef XCHAL_CP4_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP4_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP4_IDENT);
# endif
# ifdef XCHAL_CP5_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP5_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP5_IDENT);
# endif
# ifdef XCHAL_CP6_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP6_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP6_IDENT);
# endif
# ifdef XCHAL_CP7_NAME
extern const uint8_t	XCJOIN(Xthal_cp_id_,XCHAL_CP7_IDENT);
extern const uint32_t	XCJOIN(Xthal_cp_mask_,XCHAL_CP7_IDENT);
# endif
#endif




/*----------------------------------------------------------------------
				DERIVED
  ----------------------------------------------------------------------*/

#if XCHAL_HAVE_BE
#define XCHAL_INST_ILLN			0xD60F		/* 2-byte illegal instruction, msb-first */
#define XCHAL_INST_ILLN_BYTE0		0xD6		/* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1		0x0F		/* 2-byte illegal instruction, 2nd byte */
#else
#define XCHAL_INST_ILLN			0xF06D		/* 2-byte illegal instruction, lsb-first */
#define XCHAL_INST_ILLN_BYTE0		0x6D		/* 2-byte illegal instruction, 1st byte */
#define XCHAL_INST_ILLN_BYTE1		0xF0		/* 2-byte illegal instruction, 2nd byte */
#endif
/*  Belongs in xtensa/hal.h:  */
#define XTHAL_INST_ILL			0x000000	/* 3-byte illegal instruction */


/*
 *  Because information as to exactly which hardware version is targeted
 *  by a given software build is not always available, compile-time HAL
 *  Hardware-Release "_AT" macros are fuzzy (return 0, 1, or XCHAL_MAYBE):
 *  (Here "RELEASE" is now a misnomer; these are product *versions*, not the releases
 *   under which they are released.  In the T10##.# era there was no distinction.)
 */
#if XCHAL_HW_CONFIGID_RELIABLE
# define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	(XTHAL_REL_LE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	(XTHAL_REL_GE( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
# define XCHAL_HW_RELEASE_AT(major,minor)		(XTHAL_REL_EQ( XCHAL_HW_VERSION_MAJOR,XCHAL_HW_VERSION_MINOR, major,minor ) ? 1 : 0)
# define XCHAL_HW_RELEASE_MAJOR_AT(major)		((XCHAL_HW_VERSION_MAJOR == (major)) ? 1 : 0)
#else
#define XCHAL_HW_RELEASE_AT_OR_BELOW(major,minor)	(((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 : XTHAL_MAYBE)
# define XCHAL_HW_RELEASE_AT_OR_ABOVE(major,minor)	((XTHAL_REL_LE(major,minor, 1040,0) && XCHAL_HAVE_XEA2) ? 1 : XTHAL_MAYBE)
# define XCHAL_HW_RELEASE_AT(major,minor)		(((major) < 1040 && XCHAL_HAVE_XEA2) ? 0 : XTHAL_MAYBE)
# define XCHAL_HW_RELEASE_MAJOR_AT(major)		XCHAL_HW_RELEASE_AT(major,0)
#endif

/*
 * Erratum present in RH.0 hardware and RH.1 hardware.
 */
#if (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_0) || (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_1)
#define XCHAL_RH01_ERRATUM	1
#else
#define XCHAL_RH01_ERRATUM	0
#endif

/*
 * Erratum present in RH.0 through RH.2 hardware.
 */
#if (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_0) || \
    (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2016_1) || \
    (XCHAL_HW_VERSION == XTENSA_HWVERSION_RH_2017_2)
#define XCHAL_RH012_ERRATUM	1
#else
#define XCHAL_RH012_ERRATUM	0
#endif


#endif /*XTENSA_CONFIG_CORE_H*/

